In article <20050906022827.GA17648@spathi.chuq.com>
chuq@chuq.com wrote:

> this new patch works as well as mipsX_subr.S rev 1.15,
> ie. everything is fine until init starts, at which point it crashes
> with "reserved instruction in kernel mode".  that's with a GENERIC kernel;

Ok, there are several reports that "initializing pagemask" patch fixes
boot problems, I'll commit the attached patch.

Note there is another report that pagemask is 0x0 on a kernel booted
from pbsdboot on CE 2.11, but if the kernel is booted from pbsdboot
on CE 3.0, pagemask is 0x1800. Maybe that's the reason why not all
people have the same problem on VR41xx based hpcmips machines.
---
Izumi Tsutsui

Index: sys/arch/mips/include/locore.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/locore.h,v
retrieving revision 1.68
diff -u -r1.68 locore.h
--- sys/arch/mips/include/locore.h	13 Feb 2004 11:36:15 -0000	1.68
+++ sys/arch/mips/include/locore.h	7 Sep 2005 11:53:52 -0000
@@ -119,6 +119,7 @@
 
 uint32_t mips3_cp0_wired_read(void);
 void	mips3_cp0_wired_write(uint32_t);
+void	mips3_cp0_pg_mask_write(uint32_t);
 
 uint64_t mips3_ld(uint64_t *);
 void	mips3_sd(uint64_t *, uint64_t);
Index: sys/arch/mips/include/mips3_pte.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/mips3_pte.h,v
retrieving revision 1.16
diff -u -r1.16 mips3_pte.h
--- sys/arch/mips/include/mips3_pte.h	7 Aug 2003 16:28:28 -0000	1.16
+++ sys/arch/mips/include/mips3_pte.h	7 Sep 2005 11:53:52 -0000
@@ -177,3 +177,10 @@
 #define	MIPS3_PG_SIZE_16M	0x01ffe000
 #define	MIPS3_PG_SIZE_64M	0x07ffe000
 #define	MIPS3_PG_SIZE_256M	0x1fffe000
+
+/* NEC Vr41xx uses different pagemask values. */
+#define	MIPS4100_PG_SIZE_1K	0x00000000
+#define	MIPS4100_PG_SIZE_4K	0x00001800
+#define	MIPS4100_PG_SIZE_16K	0x00007800
+#define	MIPS4100_PG_SIZE_64K	0x0001f800
+#define	MIPS4100_PG_SIZE_256K	0x0007f800
Index: sys/arch/mips/mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.86
diff -u -r1.86 locore_mips3.S
--- sys/arch/mips/mips/locore_mips3.S	7 Aug 2003 16:28:32 -0000	1.86
+++ sys/arch/mips/mips/locore_mips3.S	7 Sep 2005 11:53:52 -0000
@@ -393,6 +393,20 @@
 	nop
 END(mips3_cp0_wired_write)
 
+/*
+ * void mips3_cp0_pg_mask_write(u_int32_t)
+ *
+ *	Set the value of the CP0 PG_MASK register.
+ */
+LEAF(mips3_cp0_pg_mask_write)
+	mtc0	a0, MIPS_COP_0_TLB_PG_MASK
+	COP0_SYNC
+	nop
+	nop
+	j	ra
+	nop
+END(mips3_cp0_pg_mask_write)
+
 #if defined(_MIPS_BSD_API) && \
     (_MIPS_BSD_API == _MIPS_BSD_API_N32 || _MIPS_BSD_API == _MIPS_BSD_API_LP64)
 #error mips3_ld and mips3_sd should be adjusted for N32 or LP64
Index: sys/arch/mips/mips/mips_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.178
diff -u -r1.178 mips_machdep.c
--- sys/arch/mips/mips/mips_machdep.c	1 Jun 2005 16:53:07 -0000	1.178
+++ sys/arch/mips/mips/mips_machdep.c	7 Sep 2005 11:53:52 -0000
@@ -216,10 +216,6 @@
 
 caddr_t	msgbufaddr;
 
-#if defined(MIPS3_4100)			/* VR4100 core */
-int	default_pg_mask = 0x00001800;
-#endif
-
 /* the following is used externally (sysctl_hw) */
 char	machine[] = MACHINE;		/* from <machine/param.h> */
 char	machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
@@ -886,12 +882,18 @@
 	case CPU_ARCH_MIPS3:
 	case CPU_ARCH_MIPS4:
 #if defined(MIPS3_5900)	/* XXX */
+		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
 		mips3_cp0_wired_write(0);
 		mips5900_TBIA(mips_num_tlb_entries);
 		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
 		r5900_vector_init();
 		memcpy(mips_locoresw, mips5900_locoresw, sizeof(mips_locoresw));
 #else /* MIPS3_5900 */
+#if defined(MIPS3_4100)
+		mips3_cp0_pg_mask_write(MIPS4100_PG_SIZE_4K);
+#else
+		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
+#endif
 		mips3_cp0_wired_write(0);
 		mips3_TBIA(mips_num_tlb_entries);
 		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
@@ -902,6 +904,7 @@
 #endif
 #if defined(MIPS32)
 	case CPU_ARCH_MIPS32:
+		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
 		mips3_cp0_wired_write(0);
 		mips32_TBIA(mips_num_tlb_entries);
 		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
@@ -911,6 +914,7 @@
 #endif
 #if defined(MIPS64)
 	case CPU_ARCH_MIPS64:
+		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
 		mips3_cp0_wired_write(0);
 		mips64_TBIA(mips_num_tlb_entries);
 		mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);