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On Tuesday 24 January 2006 3:33 pm, Matt Thomas wrote:
> Garrett D'Amore wrote:
> > Everyone,
> >
> > I've posted my latest diffs for Alchemy PCI support (and probably a few
> > other Alchemy fixes as well -- I didn't want to split them all out --
> > kind of painful to do that) into a diff file at
> >
> >     http://garrett.damore.org/software/netbsd/aupci.diff
> >
> > Constructive criticism is welcomed.  Flames to /dev/null.
>
> Use const more.  For instance, obiodev_t arrays should be const.
> In machdep.c, cpus[] should be const and make name [8] instead of
> a pointer.

I've made this change.

>
> be consistent.  either use obiodev_t everywhere or struct obiodev
> but don't mix them.

Looks like I started to convert to obiodev_t, but didn't bother to change a=
ll=20
of the orginal code from which this was derived.  I've completed the change=
=20
now.

>
> Add file-system TMPFS to the config files.

Hmmm... upon inspection, a lot of ports do not include this by default (e.g=
=2E=20
sparc64 doesn't even mention it, and i386 has it commented out.)  I think I=
=20
want to defer on this one for now.  If someone feels that TMPFS should be=20
enabled by default (or listed but not enabled), then that change should be=
=20
made separately.  (Reminder: I'm basically renaming the PB1000 config, and=
=20
creating two new configs to allow for board-specific PCI routing options. =
=20
This isn't really a whole new port at this point.)

> Are the interrupts evcnt'ed?

After reviewing the MIPS code, the definition of pci_intr_evcnt is not used=
=20
anywhere (at least no where that I could find), so I've removed the stub=20
definition of aupb_intr_evcnt.

All real interrupts are properly reported using evcnt at the interrupt=20
controller (ICU) and CPU levels.  The PCI driver itself never actually=20
receives interrupts directly, as we just establish a mapping at the interru=
pt=20
controller level in the pci_intr_establish code.

I think this means that the answer to your question is "yes", modified by t=
he=20
fact that I've removed the stub routine aupb_intr_evcnt.

=2D-=20
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191

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