Thank you all for your replies. I was not actually going to change 
anything. I was just curious how it works. We had a discussion at work 
about this. If one needs to mmap a large area say to access device but 
the page size is 4K and each TLB entry describes 1 page we were 
discussing how big is overhead of page faults when accessing large 
memory area because of limited number of processor tlb entries.

Regards,
Alex


Simon Burge wrote:
> Izumi Tsutsui wrote:
> 
>> simonb@NetBSD.org wrote:
>>
>>> "Alex Pelts" wrote:
>>>
>>>> I have a simple question about TLB entries. If you need to memory map 
>>>> area larger than page size does netbsd kernel allocate one tlb entry to 
>>>> describe entire area or multiple entries describing several pages of 
>>>> page size each?
>>> NetBSD only ever uses 4kB pages.
>>>
>>> If you're talking about non-KSEG0/1 kernel areas, using larger pages
>>> shouldn't be an overly difficult project...
>> How about sys/arch/mips/mips/wired_map.c?
>> (used by arc and ews4800mips etc. to map framebuffer VRAM)
> 
> I'm not sure that wired TLB entries are the answer, although I haven't
> measured this on MIPS yet.
> 
> See http://mail-index.netbsd.org/port-powerpc/2006/10/27/0000.html for
> the impact of wired TLBs on 405 PowerPC.  The quick summary is that
> overall the system got a lot more TLB misses as the number of available
> (non-wired) TLBs decreases, even where those wired TLBs were for some
> often accessed resources (system RAM in this case).
> 
> Instrumenting on MIPS will be a little more difficult, since the PowerPC
> tlb miss handler didn't need to squeeze in to 32 instructions.  I'd
> still guess that wiring isn't the answer until proven otherwise :-)
> 
> Cheers,
> Simon.
>