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removing ci_divisor_recip in mips struct cpu_info
Is there any reason to keep ci_divisor_recip in mips struct cpu_info?
I think it was introduced to implement an efficient MD microtime(9)
function (without DIV op) but it has been superceded by timecounter(9).
Is it okay to apply the attached diff?
(BTW, is it better to use u_int or uint32_t rather than u_long for
ci_cpu_freq, ci_cycles_per_hz and ci_divisor_delay since
mips3_cp0_count_read() returns uint32_t?)
---
Izumi Tsutsui
Index: sys/arch/mips/include/cpu.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpu.h,v
retrieving revision 1.89
diff -u -r1.89 cpu.h
--- sys/arch/mips/include/cpu.h 27 Feb 2008 18:26:16 -0000 1.89
+++ sys/arch/mips/include/cpu.h 23 May 2008 18:13:40 -0000
@@ -58,8 +58,6 @@
u_long ci_cpu_freq; /* CPU frequency */
u_long ci_cycles_per_hz; /* CPU freq / hz */
u_long ci_divisor_delay; /* for delay/DELAY */
- u_long ci_divisor_recip; /* scaled reciprocal of previous;
- see below */
struct lwp *ci_curlwp; /* currently running lwp */
struct lwp *ci_fpcurlwp; /* the current FPU owner */
int ci_want_resched; /* user preemption pending */
@@ -72,28 +70,6 @@
#define CPU_INFO_FOREACH(cii, ci) \
(void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next
-/*
- * To implement a more accurate microtime using the CP0 COUNT register
- * we need to divide that register by the number of cycles per MHz.
- * But...
- *
- * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT
- * and MULTU are only 12 clocks on the same CPU.
- *
- * The strategy we use is to calculate the reciprocal of cycles per MHz,
- * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the
- * HI register and have the results of the division.
- */
-#define MIPS_SET_CI_RECIPROCAL(cpu)
\
-do { \
- KASSERT((cpu)->ci_divisor_delay != 0); \
- (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \
-} while (0)
-
-#define MIPS_COUNT_TO_MHZ(cpu, count, res)
\
- __asm volatile("multu %1,%2 ; mfhi %0" \
- : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip))
-
#endif /* !_LOCORE */
#endif /* _KERNEL */
Index: sys/arch/arc/arc/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arc/arc/machdep.c,v
retrieving revision 1.110
diff -u -r1.110 machdep.c
--- sys/arch/arc/arc/machdep.c 9 Jan 2008 20:38:34 -0000 1.110
+++ sys/arch/arc/arc/machdep.c 23 May 2008 18:13:41 -0000
@@ -402,7 +402,6 @@
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
}
- MIPS_SET_CI_RECIPROCAL(curcpu());
sprintf(cpu_model, "%s %s%s",
platform->vendor, platform->model, platform->variant);
Index: sys/arch/algor/algor/algor_p4032_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/algor/algor/algor_p4032_intr.c,v
retrieving revision 1.19
diff -u -r1.19 algor_p4032_intr.c
--- sys/arch/algor/algor/algor_p4032_intr.c 28 Apr 2008 20:23:10 -0000
1.19
+++ sys/arch/algor/algor/algor_p4032_intr.c 23 May 2008 18:13:41 -0000
@@ -330,7 +330,6 @@
/* XXX assume CPU_MIPS_DOUBLE_COUNT */
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
- MIPS_SET_CI_RECIPROCAL(curcpu());
printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n",
cps, ctrdiff[2], ctrdiff[3]);
Index: sys/arch/algor/algor/algor_p5064_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/algor/algor/algor_p5064_intr.c,v
retrieving revision 1.22
diff -u -r1.22 algor_p5064_intr.c
--- sys/arch/algor/algor/algor_p5064_intr.c 28 Apr 2008 20:23:10 -0000
1.22
+++ sys/arch/algor/algor/algor_p5064_intr.c 23 May 2008 18:13:41 -0000
@@ -423,7 +423,6 @@
/* XXX assume CPU_MIPS_DOUBLE_COUNT */
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
- MIPS_SET_CI_RECIPROCAL(curcpu());
printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n",
cps, ctrdiff[2], ctrdiff[3]);
Index: sys/arch/algor/algor/algor_p6032_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/algor/algor/algor_p6032_intr.c,v
retrieving revision 1.15
diff -u -r1.15 algor_p6032_intr.c
--- sys/arch/algor/algor/algor_p6032_intr.c 28 Apr 2008 20:23:10 -0000
1.15
+++ sys/arch/algor/algor/algor_p6032_intr.c 23 May 2008 18:13:41 -0000
@@ -291,7 +291,6 @@
/* XXX assume CPU_MIPS_DOUBLE_COUNT */
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
- MIPS_SET_CI_RECIPROCAL(curcpu());
printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n",
cps, ctrdiff[2], ctrdiff[3]);
Index: sys/arch/cobalt/cobalt/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/machdep.c,v
retrieving revision 1.96
diff -u -r1.96 machdep.c
--- sys/arch/cobalt/cobalt/machdep.c 14 May 2008 13:29:27 -0000 1.96
+++ sys/arch/cobalt/cobalt/machdep.c 23 May 2008 18:13:41 -0000
@@ -253,7 +253,6 @@
/* all models have Rm5200, which is CPU_MIPS_DOUBLE_COUNT */
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
- MIPS_SET_CI_RECIPROCAL(curcpu());
physmem = btoc(memsize - MIPS_KSEG0_START);
Index: sys/arch/evbmips/evbmips/yamon.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/evbmips/yamon.c,v
retrieving revision 1.10
diff -u -r1.10 yamon.c
--- sys/arch/evbmips/evbmips/yamon.c 9 Jan 2008 20:38:35 -0000 1.10
+++ sys/arch/evbmips/evbmips/yamon.c 23 May 2008 18:13:41 -0000
@@ -153,7 +153,6 @@
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
}
- MIPS_SET_CI_RECIPROCAL(curcpu());
return ret;
}
Index: sys/arch/evbmips/malta/malta_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/malta/malta_intr.c,v
retrieving revision 1.18
diff -u -r1.18 malta_intr.c
--- sys/arch/evbmips/malta/malta_intr.c 9 Jan 2008 20:38:35 -0000 1.18
+++ sys/arch/evbmips/malta/malta_intr.c 23 May 2008 18:13:41 -0000
@@ -193,10 +193,9 @@
/* Compute the number of ticks for hz. */
curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
- /* Compute the delay divisor and reciprocal. */
+ /* Compute the delay divisor. */
curcpu()->ci_divisor_delay =
((curcpu()->ci_cpu_freq + 500000) / 1000000);
- MIPS_SET_CI_RECIPROCAL(curcpu());
/*
* Get correct cpu frequency if the CPU runs at twice the
Index: sys/arch/evbmips/atheros/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/atheros/machdep.c,v
retrieving revision 1.11
diff -u -r1.11 machdep.c
--- sys/arch/evbmips/atheros/machdep.c 8 Mar 2008 05:05:25 -0000 1.11
+++ sys/arch/evbmips/atheros/machdep.c 23 May 2008 18:13:42 -0000
@@ -213,9 +213,8 @@
curcpu()->ci_cycles_per_hz = (cntfreq + hz / 2) / hz;
- /* XXX: i don't understand this logic, it was borrowed from Malta */
+ /* Compute number of cycles per 1us (1/MHz). 0.5MHz is for roundup. */
curcpu()->ci_divisor_delay = ((cntfreq + 500000) / 1000000);
- MIPS_SET_CI_RECIPROCAL(curcpu());
}
void
Index: sys/arch/evbmips/adm5120/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbmips/adm5120/machdep.c,v
retrieving revision 1.4
diff -u -r1.4 machdep.c
--- sys/arch/evbmips/adm5120/machdep.c 9 Jan 2008 20:38:35 -0000 1.4
+++ sys/arch/evbmips/adm5120/machdep.c 23 May 2008 18:13:42 -0000
@@ -199,7 +199,6 @@
curcpu()->ci_cpu_freq = freq;
curcpu()->ci_cycles_per_hz = (freq + hz / 2) / hz / 2;
curcpu()->ci_divisor_delay = ((freq + 500000) / 1000000) / 2;
- MIPS_SET_CI_RECIPROCAL(curcpu());
}
void mach_init(int, char **, void *, void *); /* XXX */
Index: sys/arch/ews4800mips/ews4800mips/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/ews4800mips/ews4800mips/machdep.c,v
retrieving revision 1.12
diff -u -r1.12 machdep.c
--- sys/arch/ews4800mips/ews4800mips/machdep.c 28 Apr 2008 20:23:18 -0000
1.12
+++ sys/arch/ews4800mips/ews4800mips/machdep.c 23 May 2008 18:13:42 -0000
@@ -153,7 +153,6 @@
curcpu()->ci_cycles_per_hz /= 2;
curcpu()->ci_divisor_delay /= 2;
}
- MIPS_SET_CI_RECIPROCAL(curcpu());
/* Load memory to UVM */
for (i = 1; i < mem_cluster_cnt; i++) {
Index: sys/arch/mips/alchemy/au_timer.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/alchemy/au_timer.c,v
retrieving revision 1.8
diff -u -r1.8 au_timer.c
--- sys/arch/mips/alchemy/au_timer.c 9 Jan 2008 20:38:35 -0000 1.8
+++ sys/arch/mips/alchemy/au_timer.c 23 May 2008 18:13:42 -0000
@@ -119,24 +119,6 @@
((curcpu()->ci_cpu_freq + 500000) / 1000000);
/*
- * To implement a more accurate microtime using the CP0 COUNT
- * register we need to divide that register by the number of
- * cycles per MHz. But...
- *
- * DIV and DIVU are expensive on MIPS (eg 75 clocks on the
- * R4000). MULT and MULTU are only 12 clocks on the same CPU.
- * On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
- * clocks for MUL/MULTU.
- *
- * The strategy we use to to calculate the reciprocal of cycles
- * per MHz, scaled by 1<<32. Then we can simply issue a MULTU
- * and pluck of the HI register and have the results of the
- * division.
- */
- curcpu()->ci_divisor_recip =
- 0x100000000ULL / curcpu()->ci_divisor_delay;
-
- /*
* Get correct cpu frequency if the CPU runs at twice the
* external/cp0-count frequency.
*/
Index: sys/arch/sbmips/sbmips/cpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sbmips/sbmips/cpu.c,v
retrieving revision 1.17
diff -u -r1.17 cpu.c
--- sys/arch/sbmips/sbmips/cpu.c 9 Jan 2008 20:38:36 -0000 1.17
+++ sys/arch/sbmips/sbmips/cpu.c 23 May 2008 18:13:42 -0000
@@ -117,11 +117,10 @@
}
curcpu()->ci_cpu_freq = 50000000 * plldiv;
- /* Compute the delay divisor and reciprocal. */
- curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / 1000000;
- MIPS_SET_CI_RECIPROCAL(curcpu());
+ /* Compute the delay divisor. */
+ curcpu()->ci_divisor_delay = (curcpu()->ci_cpu_freq + 500000) / 1000000;
/* Compute clock cycles per hz */
- curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / hz;
+ curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2 ) / hz;
printf(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n",
curcpu()->ci_cpu_freq / 1000000,
Index: sys/arch/sgimips/dev/crime.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/dev/crime.c,v
retrieving revision 1.28
diff -u -r1.28 crime.c
--- sys/arch/sgimips/dev/crime.c 9 Jan 2008 20:38:36 -0000 1.28
+++ sys/arch/sgimips/dev/crime.c 23 May 2008 18:13:42 -0000
@@ -158,7 +158,6 @@
curcpu()->ci_cpu_freq = cps * 2 * hz;
curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz);
curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000);
- MIPS_SET_CI_RECIPROCAL(curcpu());
/* Turn on memory error and crime error interrupts.
All others turned on as devices are registered. */
Index: sys/arch/sgimips/dev/int.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/dev/int.c,v
retrieving revision 1.17
diff -u -r1.17 int.c
--- sys/arch/sgimips/dev/int.c 9 Jan 2008 20:38:36 -0000 1.17
+++ sys/arch/sgimips/dev/int.c 23 May 2008 18:13:42 -0000
@@ -187,7 +187,6 @@
curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz);
curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000);
- MIPS_SET_CI_RECIPROCAL(curcpu());
if (mach_type == MACH_SGI_IP22) {
/* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */
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