Re: Next mips bugs to examine...

[Martin Husemann <martin%duskware.de@localhost>]

On Sun, Jun 27, 2010 at 10:20:47PM +0200, Martin Husemann wrote:
> Another mystery, but unrelated, is why the emulation fix was needed not
> only for my alchemy system (where I expected it), but also for sgimips,
> where I did not expect any emulated instructions (R5000 and R10000 cpus).

And, being curios, I checked:

cpu0 at mainbus0: MIPS R5000 CPU (0x2321) Rev. 2.1 with built-in FPU Rev. 1.0
cpu0: 48 TLB entries, 16MB max page size
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
cpu0: 1024KB/32B direct-mapped write-through L2 Unified cache

but:

MachEmulateFP+18 (4442f800,cba83f60,1000002c,cba83f60) ra 801a0d74 sz 24
MachEmulateInst+100 (4442f800,cba83f60,1000002c,cba83f60) ra 80233eac sz 80
trap+6ac (4442f800,1000002c,7dea4560,7dea459c) ra 8019f7b0 sz 120
mips3_UserGenException+d8 (4442f800,1000002c,7dea4560,7dea459c) ra 0 sz 0
User-level: pid 2.1

Unfortunately gdb does not work well right now and cba83f60 seems to be in
some shared library, so I don't realy know what the instruction was.

Martin