Re: SGI O2 hangs hard constantly

[Michael <macallan%netbsd.org@localhost>]

Hello,

On Sat, 27 Feb 2021 12:49:33 +1100
matthew green <mrg%eterna.com.au@localhost> wrote:

> i believe the "error 4" means the CPU triggered an
> "illegal address", but i do not yet know what this means
> in the real world.  i have noticed that the address is 
> always in the 0x1000_0000 - 0x1400_0000 range.  i may
> try removing 2 dimms from my system, reducing it from
> 256MB to 192MB... maybe this problem occurs on R10K/
> R12K systems where memory is above the first 256MB in
> physical address?

Hmm, the CRIME manual has a section about dealing with speculative
loads from R1xk CPUs:
5.2.3 Speculative Load Workaround for CRIME 1.5

         There is a scheme to use the coherent SysCMD identifier to identify the speculative loads
         that occur because of the R10K micro-architecture that was designed for the current O2-
         R10K product. This scheme is more fully explained in [13] Moosehead R10000 Kernel
         Software but some key hardware issues have been extracted here
         for convenience.

From [13] Moosehead R10000 Kernel Software
Hardware impact summarized as:
1. Software configures cacheable TLB entries to use "noncoherent" ac-
cess mode
2. K0SEG to use "coherent" access mode
3. Hardware "rejects" K0SEG (coherent) references from 8Meg-512Meg
4. DMA buffers NOT allocated in the first 8 Meg of memory.
What Juice Does

5. For coherent block reads from 8Meg to 512Meg Juice sets a flag
called i_cmd_err. This produces a SysResp of ERR when Juice performs
the external completion response.

What does this mean for Crime 1.5?:
============================

Per the request of the DSD software team, Crime 1.5 will be made pro-
grammable to allow the range of coherent K0SEG to be adjustable from
8Meg to 32Meg in 4Meg increments. This means that HIAD needs to be
smarter and must compare the address bits from 28 down to 23 and also
look at a register that covers the choices of address range. In fact CRIME
should decode the entire address range of bits 39:23 for this implementa-
tion.

Address (or any bit set in Address bits 39:26)

25 24 23 22 K0SEG access ignored for coherent read
-- -- -- -- --------------------------------------
0 0 1 0 > 8 Meg
0 0 1 1 > 12 Meg
0 1 0 0 > 16 Meg
0 1 0 1 > 20 Meg
0 1 1 0 > 24 Meg
0 1 1 1 > 28 Meg
1 0 0 0 > 32 Meg

have fun
Michael