Re: DECstation 5000/200 timekeeping

["Maciej W. Rozycki" <macro%orcam.me.uk@localhost>]

On Tue, 26 Oct 2021, Michael wrote:

> > This really looks to me as though the clock interrupt is low enough
> > priority to get locked out by SCSI, serial, and/or Ethernet interrupts;
> > it reminds me of running NetBSD/mac68k, years ago.  Is that accurate?
> > If so, is that an attribute of the hardware, or is it something that
> > can be fixed in software?  I'm wondering if it can be fixed or if I'll
> > just have to give up on decent timekeeping on this hardware.
> 
> Hmm, that's an r4400 or somesuch, isn't it?
> Looking at the code, one difference between powerpc's clock.c and mips'
> mips3_clockintr.c is that the powerpc code calls hardclock() for every
> missed tick, while the mips code calls it once per interrupt.
> Timekeeping on both should otherwise depend on the CPU's cycle counter
> / decrementer, which both should take a lot more than a minute to
> overflow.

 Umm, the 5000/200 is R3000-based and has no high-precision timer hardware 
of any kind available.  The only clocking source available is the DS1287 
real-time clock, so the clock resolution is based on the RTC's interrupt 
frequency.  If an RTC interrupt is lost due to its handling being delayed 
by more than the interrupt's interval, then there's no way to recover.  It 
also means the clock resolution is very coarse.

 For some (though not all) of the later DECstation models a free-running 
counter register was added to the IOASIC chip that counted TURBOchannel 
clocks, and of course with any that has an R4000SC or R4400SC CPU there's 
an onchip counter register in the CPU that can be used as a reference.  
The Personal DECstation also had another counter register in its MT ASIC.

 HTH,

  Maciej