Atsushi Onoe wrote:
> 
> > I think the correct fix is to make mips3_FlushICache() convert
> > a0 into a K0 address with the proper cache index like
> > mips3_FlushDCache().  This should avoid any TLB misses in this
> > path.
> 
> > Here is the patch I had in mind.
> 
> It works fine for my NEWS5000 (R4400SC).

Did anyone else test this?  I think it should be commited so both
the regular and _2way cache ops act the same.  There is also one
part of pmap.c that this same operation can be removed from the
C code.

Comments?

jeffs