I have extensivly revamped the aic6250 driver for mach.

It mostly works fairly well now. In particular the disconnect/reconnect
works well.

I even have the synchronous negotiation apparently working. I have
debugging print outs at different stages of the negotiation and
it really does seem to do the right thing with a variety of peripherals
(one async one sync at full speed and one sync but can't handle
full speed).

However, when I actually try to start a pdma transfer in synchronous
mode, the system hangs solidly. It won't recognize the tty break
interrupt (which is a higher priority than splscsi). The pdma runs
with all interrupts disabled in data in direction so that is not
surprising, but it just runs at splscsi in data out direction, and I
*should* be able to interrupt that.

My guess is that for some reason the cpu is sitting in continuous wait
states waiting for some signal from the aic6250. I don't see that
synchronous mode on the scsi bus should affect the interface with the
microprocessor in any way, but perhaps it does.

One theory:

On datain, as I understand it, the target can send 7 reqs immediately
on going to datain phase. However, the enabling of dma mode and the
setting of the offset register doesn't happen until after the change
to data in phase. I'm not sure is the data is safely in the fifo under
these circumstances. Avoiding this is tricky. One is allowed to set up
the dma *before* the phase becomes valid, but the target changes phase
as soon as the transfer of the last phase (msg out say) is complete,
so there is no way to guarantee that some code runs between the last
byte of one phase and the change to the next phase.  Similarly with
data out, perhaps the fifo needs to be filled (somehow) before the
target goes to data out phase. I can't see how this can be done
though, for much the same reason as for datain (how do you make sure
code runs between the last transfer of the previous phase and the
change to the new phase).(*)

In either direction, if the initiator has missed REQs due to not
setting up fast enough, then it won't supply enough ACKs and the
target would be waiting until it gets enough ACKs before the transfer
is complete and the CPU would be waiting for data in the fifo (datain)
or space in the fifo (dataout).

Another theory:

One could read the specs to imply (though certainly not state directly)
that synchronous mode only works with 16 bit memory interface mode
(which we don't have).

I would appreciate it if anyone who has any knowledge anyone has
pertaining to aic6250's, the interface with the pc532 or scsi sync mode
in general shares it with me!

Ian

* Perhaps one could do something before the ack of the last byte of the
  previous phase. One can unexpectedly go out to msg in, msg out, or
  status phases, but never, I think, to datain or dataout, so this might
  actually be possible, if horrible to code.