I made some changes to the machine definition file so the following C code:

   long long add (long long a, long long b) {
       return (a + b);
   }

now generate:

_add:
	enter [r3],0
	movd 8(fp),r0
	movd 12(fp),r1
	movd 16(fp),r2
	movd 20(fp),r3
	addd r2,r0
	addcd r3,r1
	exit [r3]
	ret 0

instead of:

_add:
	enter [r3,r4,r5,r6],0
	movd 8(fp),r2
	movd 12(fp),r3
	movd 16(fp),r4
	movd 20(fp),r5
	movd r2,r0
	addd r4,r0
	cmpd r0,r2
	slod r6
	movd r3,r1
	addd r5,r1
	addd r6,r1
	exit [r6,r5,r4,r3]
	ret 0

As you can see, this is substantially better code for quad addition,
and subtraction shows nearly identical gains...  I made the pattern
only operate when both operands are in registers, since I was able
to figure out how to add 1 to a register number to get the high
half of a register pair.  (I think.)  Can anyone tell me if gcc
ALWAYS puts a quad into registers with the low half in an even
numbered register, and the high half in the next register?  Also
is there a way to specify 1 word of a quad at an offsetable address?
Then I could add from memory to r0,r1 (in this case) instead of
having the second operand loaded into r2,r3 and then added to r0,r1.

Is this something that anyone else wants?  Do you want it in the
NetBSD tree Phil?

Jon