Below is a patch for GCCs ns32k.md file to add better support for
64 bit long long values.  It implements addition, subtraction, and
negation.  Multiplication is already pretty good, and division is
done in a library routine, and I didn't want to deal with it at
this point.  (Does anyone know of any code that would use:

(long long)foo / (long long)bar or (long long)foo % (long long)bar?

This change has NOT undergone much testing.  I will be building a
new copy of the entire NetBSD source tree, after which I will feel
better about it, but for now, GCC has rebuilt itself, producing a
slightly smaller compiler, and it has built the following test
code:

long long add1x (long long x) { return (1 + x); }
long long addxy (long long x, long long y) { return (x + y); }
long long sub0x (long long x) { return (0 - x); }
long long subx1 (long long x) { return (x - 1); }
long long subxy (long long x, long long y) { return (x - y); }

these functions now compile into: (with cc -S -O [I deleted extra cruft])
_add1x:				_addxy:
	enter [],0			enter [],0
	movqd 1,r0			movd 8(fp),r0
	movqd 0,r1			movd 12(fp),r1
	addd 8(fp),r0			addd 16(fp),r0
	addcd 12(fp),r1			addcd 20(fp),r1
	exit []				exit []
	ret 0				ret 0
_sub0x:				_subx1:
	enter [],0			enter [],0
	negd 8(fp),r0			movqd -1,r0
	movqd 0,r1			movqd -1,r1
	subcd 12(fp),r1			addd 8(fp),r0
	exit []				addcd 12(fp),r1
	ret 0				exit []
					ret 0
_subxy:
	enter [],0
	movd 8(fp),r0
	movd 12(fp),r1
	subd 16(fp),r0
	subcd 20(fp),r1
	exit []
	ret 0

Do you think it's worth going for trying to play special games with
constants in the -7..7 range.  I don't think it would be any faster,
but I could probably save 4 or 8 bytes of immediate constants when
the operands are already in registers. (Or save the use of 2 registers.)

Well, please pound on this, let me know if it's faster/smaller/better/broken...
Barring suggestions for improvement or bugs, I think I will leave
it alone for a while now.  Phil, do you want me to send-pr this?

Jon Buller

Index: netbsd/gnu/usr.bin/gcc/arch/ns32k/ns32k.md
diff -c netbsd/gnu/usr.bin/gcc/arch/ns32k/ns32k.md:1.1.1.1 netbsd/gnu/usr.bin/gcc/arch/ns32k/ns32k.md:1.3
*** netbsd/gnu/usr.bin/gcc/arch/ns32k/ns32k.md:1.1.1.1	Thu Jan 25 18:06:39 1996
--- netbsd/gnu/usr.bin/gcc/arch/ns32k/ns32k.md	Tue Mar 19 20:16:43 1996
***************
*** 858,863 ****
--- 858,882 ----
    "GET_CODE (operands[1]) == CONST_INT"
    "addr %c1(sp),%0")
  
+ (define_insn "adddi3"
+   [(set (match_operand:DI 0 "general_operand" "=ro")
+ 	(plus:DI (match_operand:DI 1 "general_operand" "%0")
+ 		 (match_operand:DI 2 "general_operand" "ro")))]
+   ""
+   "*
+ {
+   output_asm_insn (\"addd %2,%0\", operands);
+   if (REG_P (operands[0]))
+     operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+   else
+     operands[0] = adj_offsettable_operand (operands[0], 4);
+   if (REG_P (operands[2]))
+     operands[2] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
+   else
+     operands[2] = adj_offsettable_operand (operands[2], 4);
+   return \"addcd %2,%0\"; 
+ }")
+ 
  (define_insn "addsi3"
    [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
  	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
***************
*** 971,976 ****
--- 990,1014 ----
    return \"adjspd %$%0\";
  }")
  
+ (define_insn "subdi3"
+   [(set (match_operand:DI 0 "general_operand" "=ro")
+ 	(minus:DI (match_operand:DI 1 "general_operand" "%0")
+ 		  (match_operand:DI 2 "general_operand" "ro")))]
+   ""
+   "*
+ {
+   output_asm_insn (\"subd %2,%0\", operands);
+   if (REG_P (operands[0]))
+     operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+   else
+     operands[0] = adj_offsettable_operand (operands[0], 4);
+   if (REG_P (operands[2]))
+     operands[2] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
+   else
+     operands[2] = adj_offsettable_operand (operands[2], 4);
+   return \"subcd %2,%0\"; 
+ }")
+ 
  (define_insn "subsi3"
    [(set (match_operand:SI 0 "general_operand" "=g")
  	(minus:SI (match_operand:SI 1 "general_operand" "0")
***************
*** 1389,1394 ****
--- 1427,1451 ----
  	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
    "TARGET_32081"
    "negf %1,%0")
+ 
+ (define_insn "negdi2"
+   [(set (match_operand:DI 0 "general_operand" "=ro")
+ 	(neg:DI (match_operand:DI 1 "general_operand" "ro")))]
+   ""
+   "*
+ {
+   output_asm_insn (\"negd %1,%0\", operands);
+   if (REG_P (operands[0]))
+     operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+   else
+     operands[0] = adj_offsettable_operand (operands[0], 4);
+   if (REG_P (operands[1]))
+     operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+   else
+     operands[1] = adj_offsettable_operand (operands[1], 4);
+   output_asm_insn (\"movqd 0,%0\", operands);
+   return \"subcd %1,%0\"; 
+ }")
  
  (define_insn "negsi2"
    [(set (match_operand:SI 0 "general_operand" "=g<")