Ian Dall <Ian.Dall@dsto.defence.gov.au> writes:

> Jon Buller <jonb@metronet.com> writes:
> 
>   > Well, that total solution can only be described as YUCK!  Would it
>   > be hard (or even possible) to allow the UART to toggle RTS when,
>   > say 10 bytes were left in the buffer, and then have the interrupt
>   > manually set RTS, and empty the fifo into the buffer, to accept 2
>   > or 3 (or even 13 or 14) more chars from slow responders?  Then when
>   > the buffer drops down to 20 or 30 bytes free, let the UART deal
>   > with RTS again.
> 
> I don't think it is really possible. The problem is FIFO overruns,
> not ring buffer overruns. The FIFO is only 4 bytes deep (8 in the
> 26C92) and the only way you can give an illusion of greater depth
> is to take stuff out of the FIFO and stick it in a ring buffer.
> Under software control you can set RTS when the ring buffer gets to
> highwater, but that is not much help if it is the FIFO which is
> overrunning.
> 
> The software control of RTS is not that bad. The z8530 code works that
> way, but it is complicated by the chip uglyness. I think I could code
> the software control pretty easilly so I might give it a go if only as
> a "proof of concept".

Oh, I think I misunderstood before.  When the FIFO overruns because
you can't get to it in time, it overruns.  Not much you can do
about it.  I thought the problem was that when the UART sets RTS,
the sender kept on going because it didn't react fast enough and
the FIFO was never emptied because the ring buffer was full and we
wanted the FIFO to keep RTS set.  That (obviously) means you just
need to add a high water mark for the ring buffer and set
RTS when you hit it.

I understand that you need to empty the full FIFO pretty fast once
RTS toggles and the interrupt comes in and if you can't do it, you
lose.  I was thinking that you just needed to empty the FIFO quick,
and keep RTS set the way it was, giving the sender 4 more character
times to recognize the fact that he should stop sending.  If the
real problem is that you can't empty the FIFO fast enough then I
don't see how moving RTS control to software could really improve
things.  Unless you set it every time you disable tty interrupts
and, as stated before, that breaks layering and modularity everywhere.

Jon Buller