On Wed, 10 Nov 1999, Toru Nishimura wrote:

> I'll dispose the small scale 'enhancement' which is now proven harmful.
> 
>   #if defined(MIPS1) && !defined(MIPS3)
>                 MachTLBUpdate(~0, entry);               /* use entryhi */
>   #else
...
> My reasoning was like this;
> 
> Whenever TLBmod exeception happens, TLB EntryHi register already has
> the TLB high part in question.  I remember now that at that time I
> expected TLB Index register already pointing the TLB entry brought the
> exception, but later concluded 'tblp' instrunction was necessary. 
> 
> I managed to reproduce the panic at the exactly same location which
> people reported, with very high load of 6-parallel make (-j 6) ran on
> /usr/src/lib/libc.  Another theory is EntryHi register has been changed
> when the 'tlbp' is about to be called.

  Um, what happens if you get a TLB miss between the TLB mod exception and
the MachTLBUpdate()?

--
Michael L. Hitch			mhitch@montana.edu
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA