>  I'm not certain what the actual CPU is in my 5000/200 and 5000/25
> without opening up the boxes.  The 5000/200 displays "CPU Rev. 2.0 with
> MIPS R3010 FPC Rev. 2.0", while the 5000/25 displays "CPU Rev. 3.0 with
> MIPS R3010 FPC Rev. 4.0".
>
>  Also, I modified the two places in trap.c to "undo" the MIPS1-only code,
> and I was able to boot that kernel on my 5000/200 without any problems.

I'll dispose the small scale 'enhancement' which is now proven harmful.

  #if defined(MIPS1) && !defined(MIPS3)
                MachTLBUpdate(~0, entry);               /* use entryhi */
  #else

The code segment above is corresponding to the following;

  LEAF(mips1_TLBUpdate)
        mfc0    v1, MIPS_COP_0_STATUS           # save the status register
        mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts

        li      v0, -1                          # check to use current entryhi
        bne     v0, a0, 1f
        nop
        tlbp
        mtc0    a1, MIPS_COP_0_TLB_LOW          # set new entrylo
        nop
        tlbwi                                   # update the entry
        j       ra
        mtc0    v1, MIPS_COP_0_STATUS
1:

My reasoning was like this;

Whenever TLBmod exeception happens, TLB EntryHi register already has
the TLB high part in question.  I remember now that at that time I
expected TLB Index register already pointing the TLB entry brought the
exception, but later concluded 'tblp' instrunction was necessary. 

I managed to reproduce the panic at the exactly same location which
people reported, with very high load of 6-parallel make (-j 6) ran on
/usr/src/lib/libc.  Another theory is EntryHi register has been changed
when the 'tlbp' is about to be called.

Tohru Nishimura