Hi,

> 	I have not performed a thorough examination, but I have mentioned
> to a few developers that the PowerPC interrupt code is flipping the MSR to
> achieve atomic operations instead of using the PowerPC load-linked
> store-conditional instructions.  I haven't looked at the memory management
> code to explore how effectively it utilizes the PowerPC MMU.

Hmm, yes, using lwarx/stwcx. may be an option with a potential to improve
performance.  Beware that our interrupt/trap handlers don't currently clear
any reservations (at least not the ones I've implemented/looked at).  This
is currently done only on process switches.  We need to change this if we
want to use lwarx/stwcx.

And yes, there are some inefficiencies in the current PowerPC pmap module.
I'm going to work on this soon.

Ciao,
Wolfgang
-- 
ws@TooLs.DE     Wolfgang Solfrank, TooLs GmbH 	+49-228-985800