Is anyone else enabling ECC on GT64260 based boards such as ev64260?

I think that the interrupt handler has some small errors in how it
handles the type feild from the fault address register. It is currently
treating 0x3 as 'reserved' when the UM for the bridge states that
this is a multiple error condition, both single bit and multiple bit
(unrecoverable) errors.

It then checks that (err == 2) and throws a panic.

I think it should (err & 2), which will cover cases 2 and 3, and
throw a panic on either.

One other small thing, it should mask off 0x3 from the address before
displaying it:

      err = addr & 0x3;
      addr &= ~0x3;

Any thoughts?

-- 
Douglas Fraser
dwfraser@onebox.com