-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, On May 21, 2008, at 16:54, Manuel Bouyer wrote:
On Wed, May 21, 2008 at 04:40:06PM -0400, Michael Lorenz wrote:
On May 21, 2008, at 15:43, Manuel Bouyer wrote:On Tue, May 20, 2008 at 08:39:09PM -0400, Michael Lorenz wrote:I didn't commit the fix yet because chuq thinks that's just a workaround for a problem elsewhere, but I couldn't find anythingremotely related in the 7400 errata list. He's got a dual 7455 which doesn't have this problem - his CPUs have L3 cache though, no idea ifMaybe it's L1 cache have different characteristics ?Both have 32kB instruction and 32kB data cache.Could it happen that this part of code has already been cached in your L1 instruction cache at this point of operations, but not on chuq's ?As far as I know the L1 caches should behave identical on both CPUs.Do you know the line size and associativity ?
Both L1 caches are 32-byte line, 8-way set associative on both the 7400 and 7455.
have fun Michael -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.7 (Darwin) iQEVAwUBSDSPRcpnzkX8Yg2nAQLtVAf7BEk8TRo4hsjFz/M1xnvqQ7/RziilrJVX GP/Y2TvJS0WdEmua64rJUX+ed2+a7u07LjaD1gMrtDmapbrqjbPgd8xRQMGHD4Wb oEdBhNK2udFrhFGhdELDP77ze45huRxq0PjWaSzxMKD+bb7tScQ4oESfdTqwbK4X TDFhCdvnFh09Sjrr6v0UyKI0w2DRywt45phoT8AXrik9iBA+A3Inbq1nigbqkTNZ 8X5e3sXkVISF7MpCFRs9TJyD2zBwXrXFagBD2NOvkrpbT0bMU4u6CpWoeH61GeBI JgpLpoVRTW4nQguac0MhY67GvLRbYf8Zet5PVvbsXjUq0xjic1wuBA== =ZzRt -----END PGP SIGNATURE-----