New Toy: TWR-P1025

[Matt Thomas <matt%3am-software.com@localhost>]

U-Boot 2011.09-rc1-02143-g5b92c1c-dirty (Apr 27 2012 - 15:03:32)

CPU0:  P1025, Version: 1.1, (0x80e40311)
Core:  E500, Version: 5.1, (0x80212051)
Clock Configuration:
       CPU0:533.333 MHz, CPU1:533.333 MHz, 
       CCB:266.667 MHz,
       DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:66.667 MHz
       QE:266.667 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: TWR-P1025 
I2C:   ready
SPI:   ready
DRAM:  Configuring DDR for 666.667 MT/s data rate
512 MiB (DDR3, 32-bit, CL=6, ECC off)
Flash: 64 MiB
L2:    256 KB enabled
MMC:  FSL_ESDHC: 0
Not a microcode
PCIe1: Root Complex of mini PCIe SLOT, no link, regs @ 0xffe0a000
PCIe1: Bus 00 - 00
PCIe2: Root Complex of TWR-ELEV PCIe SLOT, no link, regs @ 0xffe09000
PCIe2: Bus 01 - 01
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1 [PRIME], eTSEC3