Here's what Chris and I talked about wrt. disabling R5000 secondary cache
a while back; there's a couple of things to note:

	* I think (but haven't checked recently) that whatever I say here
	  about the R5k applies equally to the QED RM5200; the code should
	  probably treat both the same from this POV.
	* The SC bit in the CONFIG register isn't writable after the CPU has
	  read it's config from the EEPROM, 
	  so there's no point in setting it.
	* The SE bit may have different meaning on other CPUs, so we should
	  only clear it iff dealing with an R5000.
	* In mips/cache.c, for the R5000, we should test both SC (for cache
	  present) and SE (for cache enabled) and only set the cache-param
	  variables if the L2 cache is both present and enabled (which IIRC
	  translates to SC cleared, SE set), rather than #if 0'ing out the
	  code 8-)

I think there's also some #define that needs to be set in the sgimips 
headers to use the mips_machdep_cache_config().

--rafal

------- Forwarded Message

In message <20020918114959.GA12502@rezrov.net>, Christopher SEKIYA writes: 

[...]
On Tue, Sep 17, 2002 at 06:14:52PM -0400, Rafal Boni wrote:

> void ip32_cache_init() 
> {
> 	/* Cribbed from Loonix patches */
> 	#define R5000_CONFIG_SE		(1 << 12)
> 
> 	if (R5000) {
> 	    mips_sdcache_size = 0
> 	    mips_sdcache_line_size = 0
> 
> 	    read CoProc0 Config register
> 	    clear R5000_CONFIG_SE
> 	    write back CoProc0 Config register
> 	    nop; nop; nop			# avoid hazard (needed?)
> 	}
> }

Doing this:

void mips_machdep_cache_config(void) 
{
        u_int32_t cpu_config;

        mips_sdcache_size = 0;
        mips_sdcache_line_size = 0; 
 
        cpu_config = mips3_cp0_config_read();
        cpu_config &= 0xffffefff;
        cpu_config |= MIPS3_CONFIG_SC;
        mips3_cp0_config_write(cpu_config);
 
	__asm __volatile ("nop; nop; nop");
 
}

... and this (in mips/cache.c, line 817):

#if 0
        if ((config & MIPS3_CONFIG_SC) == 0) {
                mips_sdcache_line_size = MIPS3_CONFIG_CACHE_L2_LSIZE(config);
                if ((config & MIPS3_CONFIG_SS) == 0)
                        mips_scache_unified = 1;
        }
#else 
        mips_sdcache_line_size = 0;
#endif

(because that flag is getting reset somewhere)

results in:
[...a succesful boot on a R5000SC...]

------- End of Forwarded Message

----
Rafal Boni                                                     rafal@attbi.com
  We are all worms.  But I do believe I am a glowworm.  -- Winston Churchill