Subject: Re: Assembler multi-instruction macro in branch delay slot?
To: None <port-sgimips@NetBSD.org>
From: Havard Eidnes <he@NetBSD.org>
List: port-sgimips
Date: 01/15/2005 13:38:57 
...and there is one more in

    compile  VIOLA/locore.o
/usr/src/sys/arch/mips/mips/locore.S: Assembler messages:
/usr/src/sys/arch/mips/mips/locore.S:254: Warning: Macro instruction ex=
panded into multiple instructions in a branch delay slot

As far as I can see these are all instances similar to this
latter one:

cpu_switch_queuescan:
        lw      t0, _C_LABEL(sched_whichqs)     # look for non-empty qu=
eue
        li      t2, -1                          # t2 =3D lowest bit set=

        bne     t0, zero, 1f
>>>     lw      t3, _C_LABEL(mips_locoresw) + MIPSX_CPU_IDLE
        nop                                     # for r2000/r3000
        jal     ra, t3
        nop

where I've marked the offending line.

- H=E5vard