jacereda%gmail.com@localhost wrote:
Anyway, it looks just a simple DMA-cache issue and
the attached patch seems to fix it.
[snip]
Yes, that gets it working. Excellent!
Same here. What are the implications of that patch? Is that The Right
Thing?
As noted in bus_dma(9) BUS_DMA_COHERENT may map DMA memory into
KSEG1 on mips (which is uncached region), but "The Right Thing" is
to add a bus_dmamap_sync(9) call rather than BUS_DMA_COHERENT which is
"just a hint" as described in the MI API.
---
Izumi Tsutsui
Index: dev/crmfb.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/dev/crmfb.c,v
retrieving revision 1.25
diff -u -r1.25 crmfb.c
--- dev/crmfb.c 8 May 2008 02:10:59 -0000 1.25
+++ dev/crmfb.c 28 Jul 2008 16:35:51 -0000
@@ -304,6 +304,8 @@
for (i = 0; i < (sc->sc_tiles_x * sc->sc_tiles_y); i++) {
p[i] = ((uint32_t)v >> 16) + i;
}
+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmai.map, 0, sc->sc_dmai.size,
+ BUS_DMASYNC_PREWRITE);
sc->sc_scratch = (char *)KERNADDR(sc->sc_dma) + (0xf0000 * sc-
>sc_tiles_x);
sc->sc_linear = (paddr_t)DMAADDR(sc->sc_dma) + 0x100000 * sc-
>sc_tiles_x;