Re: should we add SH4 code to mmeye locore.S?

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

> We have two similar files evbsh3/locore.S and mmeye/locore.S with the
> major difference between one having SH4 specific code (invalidate and
> enable instruction and operand caches according to comment) and other
> (mmeye) not. However, in 2011 support was added to the newer SH4 based
> mmEye devices (see MMEYE_WLF config). Thus, the question comes if
> should add "#ifdef SH4" blocks to mmeye locore.S as well now, in case
> this code was SH4 generic and suits for both machines

I guess SH4 MMEYE kernels were tested only without cache enabled.
(7750R has 8KB VIPT cache and we need to handle annoying alias issue
 especially in port specific device drivers and bus_dma(9) functions)

So I'd say "leave it as is unless someone actually have test it."

> Additionally, shouldn't second #ifdef SH4 block be moved a bit higher,
> since XltoP2/CCR seemed to be related to SH4 blocks only:

It depends.

Both SH3/SH4 have the common virtual space segments as defined in
<sh3/cpu.h>:

---
/*
 * Logical address space of SH3/SH4 CPU.
 */
#define	SH3_PHYS_MASK	0x1fffffff

#define	SH3_P0SEG_BASE	0x00000000	/* TLB mapped, also U0SEG */
#define	SH3_P0SEG_END	0x7fffffff
#define	SH3_P1SEG_BASE	0x80000000	/* pa == va */
#define	SH3_P1SEG_END	0x9fffffff
#define	SH3_P2SEG_BASE	0xa0000000	/* pa == va, non-cacheable */
#define	SH3_P2SEG_END	0xbfffffff
#define	SH3_P3SEG_BASE	0xc0000000	/* TLB mapped, kernel mode */
#define	SH3_P3SEG_END	0xdfffffff
#define	SH3_P4SEG_BASE	0xe0000000	/* peripheral space */
#define	SH3_P4SEG_END	0xffffffff
---

The comment "CCR must be accessed from P2 area" in locore.S implies
"instructions that enable instruction cache via CCR (cache controle
 register) must be executed on non-cacheable memory."

The XLtoP2 label (0x20000000) is just used in asm as
SH3_P1SEG_TO_P2SEG() and SH3_P2SEG_TO_P1SEG() macro
in C sources as also defined in <sh3/cpu.h>:
---
#define	SH3_P1SEG_TO_P2SEG(x)	((uint32_t)(x) + 0x20000000u)
#define	SH3_P2SEG_TO_P1SEG(x)	((uint32_t)(x) - 0x20000000u)
---
so it's not quite SH4 specific, but mostly used only for SH4 cache
in primitive asm code.

---
Izumi Tsutsui