> system.  However there is one case on the Sparc motherboard where this is 
> not true - the esp SCSI chip.
> 
> A read from one of the registers on the esp chip causes it to reset its 
> state.  More specifically, I think this is the way interrupts are 
> acknowleged by the driver.  If the routine that reads from the esp 

"Slap!" (sound of hand hitting forehead).

The anser is yes and no. From memory (the manuals are upstairs and
I am downstairs getting ready to go to work) reading the CSR register
clears the interrupt. I can only remember needing to write to a
register to reset it (may be wrong). However, clearing an interrupt
is bad enough, since a request will never get answered, and yes I
suspect the process will get stuck in 'D' state.

I do not know enough about SPARC processors at that level - are window
underflows common or are they an abberation that is signalled ? If so,
when one occurs, restart any outstanding SCSI requests ...

-- 
Peter Galbavy                                           peter@wonderland.org
@ Home                                                 phone://44/973/499465
in Wonderland                              http://www.wonderland.org/~peter/
                               snail://UK/NW1_6LE/London/21_Harewood_Avenue/