> The sparc processor, upon hitting a "double" trap, will simply collapse
> into an error state. A few special wires between CPU and MMU will cause
> a processor reset in this case and set some bits in a control register.
> These bits get noticed by the firmware, which then barfs "Watchdog reset"
> (and "ok" :-).

Correct me if I'm wrong, but does the sparc processor really have a stack
in hardware?  I thought that it saves all the machine state at the time of
the trap in onchip registers and restarts at some known location.  OK, it
might get a "double" trap when it cannot access the trap handling code, but
I don't think that it can get one when accessing something on the (software
implemented) stack.

For the record, the PowerPC processor also saves the interrupt machine state
in onchip registers, but in addition it turns off the mmu before jumping to
a known location.
--
ws@TooLs.DE     (Wolfgang Solfrank, TooLs GmbH) 	+49-228-985800