On Saturday, 30 January, Eduardo E. Horvath wrote:

> > Bypass ASI's should be better from the cache standpoint also because
> > using virtual addresses pollutes an on-cpu D$ cache line. Now, we will
> > the hitting the E$ cache.
> 
> No, for H/W registers the sideffect bit in the TTE must be set so it
> bypasses both the D$ and the E$, so cache pollution is not an issue.

Right. I realised that. Of course I was wrong.

> > I think the pointer approach that you mention will hurt gcc's register
> > allocation because the immediate-indexed addressing modes will not be
> > available eg. compiler cannot generate :
> > 
> > 	ldxa	%l2, [%l1 + FOO_OFFSET] ASI_BYPASS
> > 
> > but it will have to do
> > 
> > 	set	FOO_OFFSET, %l3
> > 	ldxa	%l2, [%l1 + %l3] ASI_BYPASS
> 
> Actually, I don't think reg+reg is allowed for ldxa.  You would have to
> do:
> 
> 	add	%l1, FOO_OFFSET, %l3
> 	ldxa	[%l3] ASI_PHYS_NOCACHE, %l2

No. That is allowed. I used it in my TLB miss handlers.