[ On Monday, November 26, 2001 at 02:11:21 (-0700), Don Yuniskis wrote: ]
> Subject: Re: Hardware questions
>
> Well, one can argue that if you *need* parity, you're already
> dealing with a flakey system/design!  :>

Yeah, but the flaky part isn't where you seem to think it is.

Dynamically refreshed RAM is inherently flaky -- by design -- and far
worse than static RAM, or real core memory, for example....  :-)

Every, and I mean EVERY, system that expects to run for more than a few
minutes between reboots, _needs_ some form of hardware error detection
(or even prevention), in the memory subsystem (and the cache subsystems,
and the bus, etc.).  It's not just the refresh circuitry that you have
to trust, but the very physics of the chip die and the packaging it is
enclosed within.  At today's densities a single Alpha particle emitted
fomr some impurity in the packaging material could wipe out several bits
of data.  Even high-energy radiation that can penetrate the skin of your
machine and the chip packaging can sometimes whack a bit of data.  8-bit
parity protection of DRAM is essential, and ECC which can correct
1-bit/word errors and detect 2-bit errors is better.

Would you really run your SCSI devices with parity detection disabled
even when they work fine with it enabled?

Would you really run your UDP-based network services with UDP checksums
off?  Would you turn off TCP checksums if it were possible to do so?

Look, for example, at the hardware error detection and prevention
measures implemented in large/high-end high-availability systems
(eg. the new Sun E15K).

Why IIRC even the newer, "smaller" [:-)] Intel Pentium-III's use
technology from DEC-Alphas to do ECC on major internal buses, etc.

-- 
							Greg A. Woods

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