Just a quickie here:

Can I mix a SM71 (501-3001 w/ MXCC3.3) and an SM81 and spin
up both processors?

The reason I ask is that mbus.sunhelp.org says the SM81s have
MXCC4.x, or a single entry with just MXCC, and has notes about how
you shouldn't mix mix different cache controllers as SunOS will
probably try to enable the newer features on the older controller.

If that's the only problem, can it be worked around in the kernel?

The reason I ask is that I got the 501-3001 module for a clone SS10
someone gave me, but it appears to have a bad board.  It was cheaper
to buy a SS20 on EBay than to just try and find the one or two
replacement parts.  So I'll have the 501-3001 and an 85MHz SS20.
(Which I assume is going to be an SM81 of some sort since HyperSPARCs
only come in 80 or 90 MHz.)

Jon