At 13:38 +0200 4/22/03, Martin Husemann wrote:

>mainbus0 (root): SUNW,SPARCstation-LX: hostid 80706337
>cpu0 at mainbus0: TMS390S10 @ 50 MHz, on-chip FPU
>cpu0: physical 4K instruction (32 b/l), 2K data (16 b/l): cache enabled
>
>I didn't run crashme nor do I have a CG6 in this machine, but it runs
>-current as of a few days ago pretty reliably.

Martin,
	You do have a CG6 in that machine - it's built-in. All LX's have one.

The main difference between the MicroSPARC I and II is that they 
doubled the L1 cache size; the only machines made with MicroSPARC I's 
were the SPARC LX and the SPARCclassic.

	Erik <fair@clock.org>