Subject: Re: Dual proc SS20 not booting:
To: NetBSD port-sparc mailing list <port-sparc@netbsd.org>
From: Julian Coleman <jdc@coris.org.uk>
List: port-sparc
Date: 01/27/2004 22:07:42
> cpu0 at mainbus0: mid 8: TMS390Z50 v0 or TMS390Z55 @ 60 MHz, on-chip FPU
> cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external
> (32 b/l): cache enabled
> cpu1 at mainbus0: mid 10: TMS390Z50 v0 or TMS390Z55 @ 50 MHz, on-chip FPU
> cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external
> (32 b/l): cache enabled
> module0:
> mxcc error 0x0
> mxcc status 0xff1410002
> mxcc reset 0x4 (WATCHDOG RESET)
> module1:
> mxcc error 0x0
> mxcc status 0xff1402000
> mxcc reset 0x0
Do you know what the part numbers of the CPU's are? You could check them
against:
http://mbus.sunhelp.org/modules/
http://mbus.sunhelp.org/misc/genconf.htm
This second page notes:
8. You cannot mix cached and uncached modules on a single MBus.
9. You may or may not be able to mix modules with different L2 cache
sizes.
12. You should not mix MXCC cache-controllers of differing major
revisions, on the same MBus/XBus.
and:
13. You can mix cached SuperSPARC modules of different speeds (eg:
SM51 and SM61), if you are using Solaris 2.5.1 or a later O/S, but
you may not be free to choose which module goes in which slot.
The slot restriction only applies on those systems that can
automatically downclock the MBus. For instance, when mixing an
SM51 with an SM61 (other than 501-2571)in the SPARCstation-20
(autoselected 40/50 MHz MBus), the SM51 must go in slot 0, because
only slot 0 is used in the bus-speed-selection logic.
J
--
My other computer also runs NetBSD / Sailing at Newbiggin
http://www.netbsd.org/ / http://www.newbigginsailingclub.org/