> -----Original Message-----
> From: Tillman Hodgson [mailto:tillman@seekingfire.com] 
> Sent: 01 September 2004 14:56
> To: Gary Parker
> Cc: port-sparc@NetBSD.org
> Subject: Re: Installing Ross hypersparcs in a SS10
> 
> Howdy Gary,
> 
> That's good to hear. Are those CPUs cacheless?

Very good question!

I'm honestly not sure as I don't understand the Ross MBUS numbering scheme
(SM51 is pretty easy to interpret as opposed to RT620/625 ;)

Dmesg output as follows, I guess this means they both have 512kb cache but
I'm not certain:

cpu0 at mainbus0: mid 8: RT620/625 @ 150 MHz, on-chip FPU
cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu1 at mainbus0: mid 10: RT620/625 @ 150 MHz, on-chip FPU
cpu1: 512K byte write-back, 32 bytes/line, sw flush: cache enabled

FYI, my build of userland finished successfully at approx. 10:40, just over
25 hours after it started. This was with no '-j' flags so was essentially
only using the one CPU, not bad really...

Gary