Subject: Re: SS 5 TurboSparc upgrade cache
To: None <port-sparc@netbsd.org>
From: None <christer@a-son.net>
List: port-sparc
Date: 01/22/2005 11:29:05
On Fri, Jan 21, 2005 at 03:31:49PM +0200, Olev wrote:
> I got myself one of those 160MHz TurboSparc upgrade modules for my
> SparcStation 5. Everything works but when booting the machine only
> shows:
> 
> cpu0 at mainbus0: DVMA coherent : MB86907 @ 161 MHz, on-chip FPU
> cpu0: 16K instruction (32 b/l), 16K data (32 b/l): cache enabled
> 

This is from a Classic with a Cycle upgrade kit:
cpu0 at mainbus0DVMA coherent : MB86907 @ 171 MHz, on-chip FPU
cpu0: 16K instruction (32 b/l), 16K data (32 b/l): cache enabled

It runs NetBSD 1.6.1, or perhaps somwhere between 1.6.1 and 1.6.2

-- 
Christer O. Andersson
Odensbacken