On Sat, 22 Jan 2005 11:29:05 +0100, christer@a-son.net
<christer@a-son.net> wrote:
> On Fri, Jan 21, 2005 at 03:31:49PM +0200, Olev wrote:
> > I got myself one of those 160MHz TurboSparc upgrade modules for my
> > SparcStation 5. Everything works but when booting the machine only
> > shows:
> >
> > cpu0 at mainbus0: DVMA coherent : MB86907 @ 161 MHz, on-chip FPU
> > cpu0: 16K instruction (32 b/l), 16K data (32 b/l): cache enabled
> >
> 
> This is from a Classic with a Cycle upgrade kit:
> cpu0 at mainbus0DVMA coherent : MB86907 @ 171 MHz, on-chip FPU
> cpu0: 16K instruction (32 b/l), 16K data (32 b/l): cache enabled

Ok, so why is 512KB of cache displayed on 170MHz SS5? Is there any way
of finding out if NetBSD uses this cache on the 161MHz or not,
OpenBoot says that 512KB of secondary cache is enabled.

Olev