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Clock of cpu1 (and more) is shown incorrectly at boot in multiprocessor in -current



Hi,

Firstly, last month, I founded SPARCstation 20 from a barn in my
parents' house where I lived when I was student. This machine was 
stored when I graduated PhD cource about 10 years ago. Fortunately
it could boot Solaris, and I decided to restore and modernize it.

I installed NetBSD 6.1.4 to new HDD and upgraded to -current 
last week. Now it works fine :-) 

After I upgraded to -current, I found a simple problem that clock
of the second CPU is not correct on boot message. It's 1000 times
faster than actual clock. WoW; It's superspeed SPARC v8 :-)

Anyway, I tried to send-pr from the SPARCstation 20, however, 
mail to gnats-bugs%netbsd.org@localhost is rejected somehow reason.
# May be misconfigured to deliver to outside my domain.

So I send this problem report and its solution to this ML, in
send-pr format. 
(I thought send-pr from web, but this problem is too simple and
has only very low priority for send-pr)

Thanks.


----8<--------8<--------8<----cut here----8<--------8<----
>Submitter-Id:  net
>Originator:    Nobuyoshi SATO
>Organization:
Faculty of Software and Information Sciences,
Iwate Prefectural University, Japan.
>Confidential:  no
>Synopsis:      Clock of cpu1 is shown wrong at boot, 1000 times of actual 
>clock.
>Severity:      non-critical
>Priority:      low
>Category:      port-sparc
>Class:         sw-bug
>Release:       NetBSD 6.99.43, Jun 3, 2014.
>Environment:

Hardware:
SPARCstation 20, with two 75MHz SuperSPARC-II MBus modules. Sun part numbers
for two CPU modules are 501-2520 and 501-3001.
OpenBoot PROM 2.25.
        
System: NetBSD balalaika.db.soft.iwate-pu.ac.jp 6.99.43 NetBSD 6.99.43 
(BALALAIKA) #5: Wed Jun 4 12:44:44 JST 2014 
nobu-s%balalaika.db.soft.iwate-pu.ac.jp@localhost:/usr/src/sys/arch/sparc/compile/BALALAIKA
 sparc
Architecture: sparc
Machine: sparc

>Description:

CPU clock of cpu1 is shown 1000 times faster when booting incorrectly,
as following:

cpu0 at mainbus0: mid 8: TMS390Z50 v0 or TMS390Z55 @ 75  MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b
/l): cache enabled
cpu1 at mainbus0: mid 10: TMS390Z50 v0 or TMS390Z55 @ 75000  MHz, on-chip FPU
cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b
/l): cache enabled

The message for cpu0 is shown by following at cpu_attach() in line 439, in 
sys/arch/sparc/sparc/cpu.c:

        snprintf(buf, sizeof buf, "%s @ %s MHz, %s FPU",
                cpi->cpu_longname, clockfreq(cpi->hz / 1000), cpi->fpu_name);

And the message for cpu1 is shwon by following at cpu_attach_non_boot() in
line 528 in the same file:

        printf(": %s @ %s MHz, %s FPU\n", cpi->cpu_longname,
                clockfreq(cpi->hz), cpi->fpu_name);

So, it's just to forget to divide cpi->hz by 1000. I also confirmed the
raw values for cpi-hz for the cpu0 and cpu1 are the same.

>How-To-Repeat:
Just boot with multiprocessor enabled kernel of NetBSD-current on
(any) multiprocessor machine.

>Fix:
Just add to divide cpi->hz by 1000 in cpu_attach_non_boot() in
sys/arch/sparc/sparc/cpu.c following:

--- cpu.c.orig  2014-06-02 12:14:28.000000000 +0900
+++ cpu.c       2014-06-04 12:41:53.000000000 +0900
@@ -526,7 +526,7 @@
        /* Now start this CPU */
        cpu_spinup(cpi);
        printf(": %s @ %s MHz, %s FPU\n", cpi->cpu_longname,
-               clockfreq(cpi->hz), cpi->fpu_name);
+               clockfreq(cpi->hz / 1000), cpi->fpu_name);
 
        cache_print(sc);
 
----8<--------8<--------8<----cut here----8<--------8<----


Lecturer / Faculty of Software & Info. Sci., Iwate Prefectural Univ.
Nobuyoshi Sato, Ph.D / nobu-s%iwate-pu.ac.jp@localhost / +81-19-694-2612


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