Re: 10_BETA panic on Ultra 1

[Martin Husemann <martin%duskware.de@localhost>]

On Fri, Aug 25, 2023 at 07:41:55AM +0000, Taylor R Campbell wrote:
> But how soft interrupts get disaptched before the higher-priority hard
> interrupts have returned is unclear.  That looks like the
> sparc64-specific bug here.

OK, let's try to find it.

> If something is doing spl0 that would explain it, or if something is
> broken in splx or splsoft* or mutex_exit or something that could also
> explain it.  But it's weird that it happens only with esp(4) and not
> with every disk driver.

Nothing is doing spl0 - I added the equivalent of 

	KASSERT(newpil > 0 || !cpu_intr_p())

to all spl* inline functions and none did fire.

Also the trapframe claims we are at PIL 4 when the softint kassert fires:

db{0}> mach tf
Trapframe 0x184d6c0:    tstate: 82000602        pc: 10348a4     npc: 10348a8
y: 0    pil: 4  oldpil: 4       fault: 13a43d9  tt: 101 Globals:
00000001a2413021 0000000000000001 0000000001c14000 0000000000000000
0000000000000001 0000000000000000 0000000000000000 0000000000000000
outs:
0000000001878d58 0000000101bc3140 00ff0f0000000001 0000000000000000
00000000e0048000 000000000180b000 00000001a24130d1 0000000001264440

Martin