Re: Some more patches for GCC on NetBSD/VAX coming soon...

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

> But half the point in the original example code was that you can have
> any instruction there,

Not quite - only a single-word instruction.  Lots of PDP-11
instructions are (or at least can be) two words long; while my PDP-11
is a bit weak, I think some can even be three words long.

> which then can be skipped by this clever "prefix".  This general
> approach will not work on a VAX.

True; it is far more restricted on the VAX.  There _are_ single-byte
instructions, but not many.  The list I have at readiest hand shows
eight, of which three are kernel-only (HALT, LDPCTX, SVPCTX) and none
of the rest (BPT, NOP, REI, RET, RSB) strike as very useful in this
trick - all but NOP provoke some form of unusual control flow.

However, on the VAX, if the skipped instruction is two, four, or eight
bytes long, doing the same trick with immediate mode word, long, or
quad data might work usefully.  Two bytes representing TSTL (PC)+ can
operate as a skip prefix (with condition code fiddling) for any
four-byte instruction; if the skipped instruction is BICPSW or BISPSW
instruction with an immediate-mode operand it would be a rough analog
of the quoted PDP-11 trick.  But I'm not sure how useful it would be.
VMS used to use the condition codes on return from some routines, IIRC;
I don't know of any Unixy ABI that did, but I don't know many Unixy VAX
ABIs, so that doesn't mean much.

Or perhaps DD 8F B9 (or B8) 8F xx 00.  There are possibilities....

There probably are a handful of more complicated overlaps for which
multiple sequences are useful, but I daresay not very many.

I'm reminded of the logically consistent interpretation on the SPARC of
putting a delayed branch in a delay slot: it executes one instruction
at the target of the first branch before picking up at the second
branch target.  (The hardware doesn't actually do that; instead, it
faults.  Pesky implementors expecting to have it easy. :-)

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