Re: Interested in USB for TURBOchannel (slhci at tc)?

[Felix Deichmann <m4j0rd0m0%gmail.com@localhost>]

2016-04-07 21:29 GMT+02:00 Tobias Nygren <tnn%netbsd.org@localhost>:
> I'll take 5 pieces at this price point but I would like to humbly
> request for verilog/vhdl source code to be included with the hardware
> and that if possible any unused GPIO pins on the CLPD device be routed
> to an unpopulated pin header along with power and gnd so that the
> boards may be repurposed and extended for other turbochannel
> shenanigans.

Great, a high-roller. :)

The CPLD variant I wanted to use has 100 pins, from which only 64 + 10
"special purpose" are usable as GPIO. Subtract 33 + 5 for TC, 8 + 6
for SL811HS, and around 5 for LEDs and jumpers (LEDs are nice to have
I think, but won't be visible when the enclosure is closed).
Maybe only 8+ GPIOs could be realized. More or much more will require
a larger CPLD (package, macrocells, cost) and seems to shift the scope
of the project severely.

TC provides 12 V and 5 V (I only wanted to use 5 V...). 3.3 V and 1.8
V are also required and obtained from 5 V by LDOs. It's a little
voltage converter board, too. :)
I planned using a (cheaper) two-layer PCB, which can be done when
carefully designed, but routing additional power to your pin header
(you would want all of course...?) can make things ugly quickly. I
will see what I can do. Single test points (you can solder in a single
pin) spread across the PCB for all the voltages are planned anyway for
acceptance testing.

Giving away my VHDL code is a point I still think about. I have my
fights... It is not necessary for people who want USB flat as per the
project's definition, as the CPLD is like just another dedicated IC.
For the people interested in extending the option's original scope, I
understand it would be valuable. But then you could also design your
own board altogether, maybe focus on extendability. TC is no rocket
science, all specs are still available from HP's FTP server and it was
designed as open bus since ever.
I see no problem in providing and maintaining the JED files for the
CPLD. For the source, gimme time.

What I also started writing together with developing the option is
documentation (manual/specification, many details on timings etc.).
This will also be made available of course.

Regards,
Felix