Re: New Vax - future directions :-)

[Paul Koning <paulkoning%comcast.net@localhost>]

> On Jul 5, 2021, at 6:29 PM, Jason Thorpe <thorpej%me.com@localhost> wrote:
> 
> 
>> On Jul 5, 2021, at 3:17 PM, Johnny Billquist <bqt%update.uu.se@localhost> wrote:
>> 
>> On 2021-07-05 23:03, Jason Thorpe wrote:
>>>> On Jul 5, 2021, at 12:18 PM, Mouse <mouse%Rodents-Montreal.ORG@localhost> wrote:
>>>> 
>>>> 
>>>> It clears R0 and R1.  On VAX-32, that is.  It remains to be determined
>>>> what it would do on VAX-64 (in 64-bit mode, if the hardware is to be
>>>> dual-mode).  Personally, I would say it should clear just R0 (but all
>>>> 64 bits of it).
>>> IMO, CLRQ should be disallowed in 32-bit mode.
>> 
>> I think you are about 45 years late for that one. :-D
> 
> Ok, let me re-state… “for any Q insn that does not already exist, trying to use it in 32-bit mode should cause an illegal insn fault”.
> 
> The idea that an operation that takes a single register as an argument would operate on two is, frankly, stupid.

One might argue that, but architectures that do this go back at least as far as 1958 (Electrologica X-1).  Some well known examples where this is done include the CDC 6000 series, the PDP11, and MIPS.  The fact that CDC does this shows clearly that it can be done without significant problems in instruction issue scheduling.

	paul