Re: KA630: how does console I/O actually work?

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

> I think NetBSD is depending on taking the interrupt being enough to
> clear the interrupt.  [...]

> And, indeed, that's what I see in simh's code.  [...]

A relevant comment in myu emulator code says

   * The info above (apparently from EK-KA630-UG-001) is at least
   *  partially false.  The IE bits in RXCS and TXCS are not enables
   *  for level-triggered interrupts; rather, the interrupts are
   *  edge-triggered, interrupting whenever the function "IE & DONE" 
   *  (RXCS) or "IE & RDY" (TXCS) changes from 0 to 1.  This comes from
   *  the VARM and also seems to be how NetBSD's kernel treats it.
   *  This is why cons_intr exists: to record these interrupt requests.

I went looking for the basis for the "comes from the VARM" part.

Using EL-00032-00-decStd32_Jan90.txt as my reference, this appears to
refer to tables 10-4 and 10-6, on pages 10-35 and 10-36.  Table 10-4
says, of RXCS's IE bit,

      interrupt enable  <6>     Read/write.     Cleared     by     processor
                                initialization  and  by  being written zero.
                                If interrupt enable is set by software while
                                RXDB  Ready  is  already set, or if ready is
                                set by the console while Interrupt enable is
                                already  set, then an interrupt is requested
                                at IPL 14 (hex).  That is, an  interrupt  is
                                requested  whenever  the function {interrupt
                                enable AND ready} changes from 0 to 1.

Note in particular the last sentence.

Table 10-6 uses similar language when describing TXCS's IE bit.

I suspect these are the VARM reference I had for the idea that these
interrupts are, in at least this respect, edge-triggered.

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