Re: CVS commit: [matt-nb5-mips64] src/sys/arch/mips/mips

[Masao Uebayashi <uebayasi%tombi.co.jp@localhost>]

> @@ -225,11 +226,18 @@
>  {
>       KASSERT(!CPU_IS_PRIMARY(ci));
>       KASSERT(ci->ci_data.cpu_idlelwp != NULL);
> +     KASSERT(cold);

We should have a more descriptive variable to represent systems global state...
(Define state transition strictly too.)

Masao

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Masao Uebayashi / Tombi Inc. / Tel: +81-90-9141-4635