Re: CVS commit: src/sys/dev/sdmmc

[Greg Troxel <gdt%ir.bbn.com@localhost>]

On Jul 17, 2012, at 0925 , Matt Thomas wrote:

> 
> On Jul 17, 2012, at 5:39 AM, Greg Troxel wrote:
> 
>> 
> 
> 0x30 is aligned and that is the address that is read from a 32-bit access.

Not enough coffee - I was reading hex as decimal :-)

>> In the non-32 case, it seems that the EINTR register is read and then
>> written back exactly if the error bit is set in the NINTR register.  In
>> the 32 case, it seems that the SDHC_ERROR_INTERRUPT bit is set in NINTR
>> if any bits are set in EINTR, in addition to writing both.
>> 
>> So while I see the point that the |= into status is effectively a dead
>> store,
>> 
>> it seems odd to have bits set in SDHC_EINTR_STATUS without
>> SDHC_ERROR_INTERRUPT set in SDHC_NINTR_STATUS, and
>> the two code paths seem different still
> 
> This is because the ESDHC doesn't set SDHC_ERROR_INTERRUPT in its
> register since you've read SDHC_EINTR_STATUS and can see those bits
> directly.  So, for the sdhc driver, it needs to be emulated.

So the 4-byte read causes the SDHC_ERROR_INTERRUPT not to get set because
the same read reads EINTR_STATUS, or the chip that's in systems that need
4-byte reads is different (ESDHC vs SDHC?)?

>> I'm curious if you've been seeing bits in EINTR without ERROR in NINTR,
>> and what the symptoms are that provoked this fix - I have a system with
>> an sdhc (on evbppc/P2020) that mostly works but has occasional write
>> errors.
> 
> That is exactly what the ESDHC on the P2020 does.

Thanks; that could be our issue then.