Re: CVS commit: src/external/gpl3/gcc/dist/gcc/config/i386

[David Laight <david%l8s.co.uk@localhost>]

On Sat, Oct 06, 2012 at 02:10:46PM +0000, Joerg Sonnenberger wrote:
> Module Name:  src
> Committed By: joerg
> Date:         Sat Oct  6 14:10:46 UTC 2012
> 
> Modified Files:
>       src/external/gpl3/gcc/dist/gcc/config/i386: i386.h
> 
> Log Message:
> PR 46978: ICE on spilling MMX registers
> 
> GCC/i386 has code to lower the required alignment for long long to 32bit
> as the CPU doesn't need more. It is also using the same mode for setting
> up the MMX registers and in turn, the stack slots reserved for spilling
> require 32bit alignment. The actual vector types used keep the original
> 64bit alignment, so when the compiler wants to spill a MMX register, it
> hits an assertion. Fix this by using the vector type as raw type for MMX
> registers.

Doesn't that enforce a 64bit alignment when it isn't needed?
Or have I misread the commit message?
Misaligned transfers for stack slots for MMX are actually fine.

Only the 128bit (and larger) accesses have to be aligned.

The performance penalty of misaligned 64bit transfers really is best
avoided by maintaining the stack alignment - and assuming it won't
get misaligned.

I suspect that the 'sub %sp,n' use to allocate a stack frame has
hardware optimisations that are absent from the 'and %sp,~7' needed
to realign it.

        David

-- 
David Laight: david%l8s.co.uk@localhost