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[src/trunk]: src/usr.sbin/cpuctl/arch add aarch64 support for cp...
details: https://anonhg.NetBSD.org/src/rev/7f0717a9c736
branches: trunk
changeset: 318714:7f0717a9c736
user: ryo <ryo%NetBSD.org@localhost>
date: Thu May 03 15:47:36 2018 +0000
description:
add aarch64 support for cpuctl identify.
diffstat:
usr.sbin/cpuctl/arch/aarch64.c | 619 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 619 insertions(+), 0 deletions(-)
diffs (truncated from 623 to 300 lines):
diff -r e6d467f3e422 -r 7f0717a9c736 usr.sbin/cpuctl/arch/aarch64.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/usr.sbin/cpuctl/arch/aarch64.c Thu May 03 15:47:36 2018 +0000
@@ -0,0 +1,619 @@
+/* $NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $ */
+
+/*
+ * Copyright (c) 2018 Ryo Shimizu <ryo%nerv.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+#ifndef lint
+__RCSID("$NetBSD: aarch64.c,v 1.1 2018/05/03 15:47:36 ryo Exp $");
+#endif /* no lint */
+
+#include <sys/types.h>
+#include <sys/cpuio.h>
+#include <sys/sysctl.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <inttypes.h>
+#include <err.h>
+
+#include <arm/cputypes.h>
+#include <aarch64/armreg.h>
+
+#include "../cpuctl.h"
+
+struct cpuidtab {
+ uint32_t cpu_partnum;
+ const char *cpu_name;
+ const char *cpu_class;
+ const char *cpu_architecture;
+};
+
+struct impltab {
+ uint32_t impl_id;
+ const char *impl_name;
+};
+
+struct fieldinfo {
+ int bitpos;
+ int bitwidth;
+ const char *name;
+ const char * const *info;
+};
+
+
+#define CPU_PARTMASK (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
+const struct cpuidtab cpuids[] = {
+ { CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
+ { CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
+ { CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
+ { CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
+ { CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A" },
+ { CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A" }
+};
+
+const struct impltab implids[] = {
+ { CPU_ID_ARM_LTD, "ARM Limited" },
+ { CPU_ID_BROADCOM, "Broadcom Corporation" },
+ { CPU_ID_CAVIUM, "Cavium Inc." },
+ { CPU_ID_DEC, "Digital Equipment Corporation" },
+ { CPU_ID_INFINEON, "Infineon Technologies AG" },
+ { CPU_ID_MOTOROLA, "Motorola or Freescale Semiconductor Inc." },
+ { CPU_ID_NVIDIA, "NVIDIA Corporation" },
+ { CPU_ID_APM, "Applied Micro Circuits Corporation" },
+ { CPU_ID_QUALCOMM, "Qualcomm Inc." },
+ { CPU_ID_SAMSUNG, "SAMSUNG" },
+ { CPU_ID_TI, "Texas Instruments" },
+ { CPU_ID_MARVELL, "Marvell International Ltd." },
+ { CPU_ID_APPLE, "Apple Inc." },
+ { CPU_ID_FARADAY, "Faraday Technology Corporation" },
+ { CPU_ID_INTEL, "Intel Corporation" }
+};
+
+/* ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 */
+struct fieldinfo id_aa64pfr0_fieldinfo[] = {
+ {
+ .bitpos = 0, .bitwidth = 4, .name = "EL0",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No EL0",
+ [1] = "AArch64",
+ [2] = "AArch64/AArch32"
+ }
+ },
+ {
+ .bitpos = 4, .bitwidth = 4, .name = "EL1",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No EL1",
+ [1] = "AArch64",
+ [2] = "AArch64/AArch32"
+ }
+ },
+ {
+ .bitpos = 8, .bitwidth = 4, .name = "EL2",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No EL2",
+ [1] = "AArch64",
+ [2] = "AArch64/AArch32"
+ }
+ },
+ {
+ .bitpos = 12, .bitwidth = 4, .name = "EL3",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No EL3",
+ [1] = "AArch64",
+ [2] = "AArch64/AArch32"
+ }
+ },
+ {
+ .bitpos = 16, .bitwidth = 4, .name = "FP",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "Floating Point",
+ [15] = "No Floating Point"
+ }
+ },
+ {
+ .bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "Advanced SIMD",
+ [15] = "No Advanced SIMD"
+ }
+ },
+ {
+ .bitpos = 24, .bitwidth = 4, .name = "GIC",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No GIC",
+ [1] = "GICv3"
+ }
+ },
+ { .bitwidth = 0 } /* end of table */
+};
+
+/* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
+struct fieldinfo id_aa64isar0_fieldinfo[] = {
+ {
+ .bitpos = 4, .bitwidth = 4, .name = "AES",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No AES",
+ [1] = "AESE/AESD/AESMC/AESIMC",
+ [2] = "AESE/AESD/AESMC/AESIMC+PMULL/PMULL2"
+ }
+ },
+ {
+ .bitpos = 8, .bitwidth = 4, .name = "SHA1",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No SHA1",
+ [1] = "SHA1C/SHA1P/SHA1M/SHA1H/SHA1SU0/SHA1SU1"
+ }
+ },
+ {
+ .bitpos = 12, .bitwidth = 4, .name = "SHA2",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No SHA2",
+ [1] = "SHA256H/SHA256H2/SHA256SU0/SHA256U1"
+ }
+ },
+ {
+ .bitpos = 16, .bitwidth = 4, .name = "CRC32",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No CRC32",
+ [1] = "CRC32B/CRC32H/CRC32W/CRC32X"
+ "/CRC32CB/CRC32CH/CRC32CW/CRC32CX"
+ }
+ },
+ { .bitwidth = 0 } /* end of table */
+};
+
+/* ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0 */
+struct fieldinfo id_aa64mmfr0_fieldinfo[] = {
+ {
+ .bitpos = 0, .bitwidth = 4, .name = "PARange",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "32bits/4GB",
+ [1] = "36bits/64GB",
+ [2] = "40bits/1TB",
+ [3] = "42bits/4TB",
+ [4] = "44bits/16TB",
+ [5] = "48bits/256TB"
+ }
+ },
+ {
+ .bitpos = 4, .bitwidth = 4, .name = "ASIDBit",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "8bits",
+ [2] = "16bits"
+ }
+ },
+ {
+ .bitpos = 8, .bitwidth = 4, .name = "BigEnd",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No mixed-endian",
+ [1] = "Mixed-endian"
+ }
+ },
+ {
+ .bitpos = 12, .bitwidth = 4, .name = "SNSMem",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No distinction B/W Secure and Non-secure Memory",
+ [1] = "Distinction B/W Secure and Non-secure Memory"
+ }
+ },
+ {
+ .bitpos = 16, .bitwidth = 4, .name = "BigEndEL0",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No mixed-endian at EL0",
+ [1] = "Mixed-endian at EL0"
+ }
+ },
+ {
+ .bitpos = 20, .bitwidth = 4, .name = "TGran16",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No 16KB granule",
+ [1] = "16KB granule"
+ }
+ },
+ {
+ .bitpos = 24, .bitwidth = 4, .name = "TGran64",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No 64KB granule",
+ [15] = "64KB granule"
+ }
+ },
+ {
+ .bitpos = 28, .bitwidth = 4, .name = "TGran4",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "4KB granule",
+ [15] = "No 4KB granule"
+ }
+ },
+ { .bitwidth = 0 } /* end of table */
+};
+
+/* MVFR0_EL1 - Media and VFP Feature Register 0 */
+struct fieldinfo mvfr0_fieldinfo[] = {
+ {
+ .bitpos = 0, .bitwidth = 4, .name = "SIMDreg",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No SIMD",
+ [1] = "16x64-bit SIMD",
+ [2] = "32x64-bit SIMD"
+ }
+ },
+ {
+ .bitpos = 4, .bitwidth = 4, .name = "FPSP",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No VFP support single precision",
+ [1] = "VFPv2 support single precision",
+ [2] = "VFPv2/VFPv3/VFPv4 support single precision"
+ }
+ },
+ {
+ .bitpos = 8, .bitwidth = 4, .name = "FPDP",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "No VFP support double precision",
+ [1] = "VFPv2 support double precision",
+ [2] = "VFPv2/VFPv3/VFPv4 support double precision"
+ }
+ },
+ {
+ .bitpos = 12, .bitwidth = 4, .name = "FPTrap",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "VFPv2 support exception trapping",
+ [1] = "VFPv2/VFPv3/VFPv4 support exception trapping"
+ }
+ },
+ {
+ .bitpos = 16, .bitwidth = 4, .name = "FPDivide",
+ .info = (const char *[16]) { /* 16=4bit */
+ [0] = "VDIV not supported",
+ [1] = "VDIV supported"
+ }
+ },
+ {
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