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[src/trunk]: src/sys/arch/powerpc copy HID1 from the boot CPU to secondary CP...
details: https://anonhg.NetBSD.org/src/rev/4b28d4035915
branches: trunk
changeset: 319319:4b28d4035915
user: macallan <macallan%NetBSD.org@localhost>
date: Fri May 25 23:00:34 2018 +0000
description:
copy HID1 from the boot CPU to secondary CPUs as well on 64bit CPUs
now the 2nd CPU on my G5s runs at full speed
diffstat:
sys/arch/powerpc/include/cpu.h | 3 ++-
sys/arch/powerpc/oea/cpu_subr.c | 6 ++++--
2 files changed, 6 insertions(+), 3 deletions(-)
diffs (51 lines):
diff -r 7efa6aed9b0a -r 4b28d4035915 sys/arch/powerpc/include/cpu.h
--- a/sys/arch/powerpc/include/cpu.h Fri May 25 20:48:54 2018 +0000
+++ b/sys/arch/powerpc/include/cpu.h Fri May 25 23:00:34 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.105 2018/05/04 17:01:29 macallan Exp $ */
+/* $NetBSD: cpu.h,v 1.106 2018/05/25 23:00:34 macallan Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@@ -164,6 +164,7 @@
uint32_t hatch_tbl;
#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
uint64_t hatch_hid0;
+ uint64_t hatch_hid1;
uint64_t hatch_hid4;
uint64_t hatch_hid5;
#else
diff -r 7efa6aed9b0a -r 4b28d4035915 sys/arch/powerpc/oea/cpu_subr.c
--- a/sys/arch/powerpc/oea/cpu_subr.c Fri May 25 20:48:54 2018 +0000
+++ b/sys/arch/powerpc/oea/cpu_subr.c Fri May 25 23:00:34 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.93 2018/05/04 17:01:29 macallan Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.94 2018/05/25 23:00:34 macallan Exp $ */
/*-
* Copyright (c) 2001 Matt Thomas.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.93 2018/05/04 17:01:29 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.94 2018/05/25 23:00:34 macallan Exp $");
#include "opt_ppcparam.h"
#include "opt_ppccache.h"
@@ -1316,6 +1316,7 @@
h->hatch_hid0 = mfspr(SPR_HID0);
#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
+ h->hatch_hid1 = mfspr(SPR_HID1);
h->hatch_hid4 = mfspr(SPR_HID4);
h->hatch_hid5 = mfspr(SPR_HID5);
printf("HIDs: %016llx %016llx\n", h->hatch_hid4, h->hatch_hid5);
@@ -1439,6 +1440,7 @@
if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) {
mtspr64(SPR_HID0, h->hatch_hid0);
+ mtspr64(SPR_HID1, h->hatch_hid1);
mtspr64(SPR_HID4, h->hatch_hid4);
mtspr64(SPR_HID5, h->hatch_hid5);
mtspr64(SPR_HIOR, 0);
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