[src/trunk]: src/sys/dev/pci make this work on rv350 chips found in last gene...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7b191c609630
branches:  trunk
changeset: 319872:7b191c609630
user:      macallan <macallan%NetBSD.org@localhost>
date:      Thu Jun 14 17:41:27 2018 +0000

description:
make this work on rv350 chips found in last generation *Books
Needs testing on non-Apple hardware.

diffstat:

 sys/dev/pci/radeonfb.c |  44 +++++++++++++++++++++++++++++++++-----------
 1 files changed, 33 insertions(+), 11 deletions(-)

diffs (124 lines):

diff -r 5af888b18fd4 -r 7b191c609630 sys/dev/pci/radeonfb.c
--- a/sys/dev/pci/radeonfb.c    Thu Jun 14 16:17:18 2018 +0000
+++ b/sys/dev/pci/radeonfb.c    Thu Jun 14 17:41:27 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: radeonfb.c,v 1.95 2018/06/06 01:49:08 maya Exp $ */
+/*     $NetBSD: radeonfb.c,v 1.96 2018/06/14 17:41:27 macallan Exp $ */
 
 /*-
  * Copyright (c) 2006 Itronix Inc.
@@ -70,7 +70,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.95 2018/06/06 01:49:08 maya Exp $");
+__KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.96 2018/06/14 17:41:27 macallan Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -873,7 +873,7 @@
                /* N.B.: radeon wants 64-byte aligned stride */
                dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8;
                dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN);
-               DPRINTF(("stride: %d\n", dp->rd_stride));
+               DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx));
 
                dp->rd_offset = sc->sc_fboffset * i;
                dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt,
@@ -1643,6 +1643,13 @@
        DPRINTF(("dot clock: %u\n", dotclock));
        for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
                if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) continue;
+               /*
+                * XXX
+                * the rv350 in my last generation 14" iBook G4 produces
+                * garbage with dividers > 4. No idea if this is a hardware
+                * limitation or an error in the divider table.
+                */
+               if ((sc->sc_family == RADEON_RV350) && (div > 4)) continue;
                outfreq = div * dotclock;
                if ((outfreq >= sc->sc_minpll) &&
                    (outfreq <= sc->sc_maxpll)) {
@@ -1833,6 +1840,12 @@
                        sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I;
                        sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
                        sc->sc_ports[0].rp_number = 0;
+                       sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
+                       sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE;
+                       sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN;
+                       sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE;
+                       sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
+                       sc->sc_ports[1].rp_number = 1;
                } else if IS_MOBILITY(sc) {
                        /* default, port 0 = internal TMDS, port 1 = CRT */
                        sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
@@ -2035,25 +2048,38 @@
 {
        uint32_t        pbit = 0;
        uint32_t        feed = 0;
-       uint32_t        data, refdiv, div0;
+       uint32_t        data, refdiv, div0, r2xxref;
 
        radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags);
 
        if (crtc == 0) {
 
                refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV);
-               if (IS_R300(sc)) {
+               
+               /*
+                * XXX
+                * the RV350 in my last generation iBook G4 behaves like an
+                * r2xx here - try to detect that and not screw up the reference
+                * divider.
+                * xf86-video-radeon just skips PLL programming altogether
+                * on iBooks, probably for this reason.
+                */
+               r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv;
+               if (IS_R300(sc) && (r2xxref != refdiv)) {
                        refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) |
                            (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT);
                } else {
                        refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) |
                            sc->sc_refdiv;
                }
+               DPRINTF(("refdiv %08x\n", refdiv));
                div0 = GETPLL(sc, RADEON_PPLL_DIV_0);
+               DPRINTF(("div0 %08x\n", div0));
                div0 &= ~(RADEON_PPLL_FB3_DIV_MASK |
                    RADEON_PPLL_POST3_DIV_MASK);
                div0 |= pbit;
                div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK);
+               DPRINTF(("div0 %08x\n", div0));
 
                if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) &&
                    (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) {
@@ -3026,10 +3052,8 @@
        }
        if (rv == GC_ADD) {
                glyphcache_add(&dp->rd_gc, c, xd, yd);
-       } else
-               if (attr & 1)
-                       radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
-
+       } else if (attr & 1)
+               radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
 }
 
 static void
@@ -3157,7 +3181,6 @@
        } else
                if (attr & 1)
                        radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
-
 }
 
 /*
@@ -3321,7 +3344,6 @@
            RADEON_DST_Y_TOP_TO_BOTTOM);
        PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
        PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
-
 }
 
 static void