[src/trunk]: src/sys/arch/x86/include AMD L3 cache association bitfield is no...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c01589c1bff8
branches:  trunk
changeset: 321340:c01589c1bff8
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Mar 12 07:35:45 2018 +0000

description:
AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

diffstat:

 sys/arch/x86/include/cacheinfo.h |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (18 lines):

diff -r 4bb662f475cf -r c01589c1bff8 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Mon Mar 12 07:12:54 2018 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Mon Mar 12 07:35:45 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.26 2018/03/12 07:35:45 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -140,7 +140,7 @@
 
 /* L3 Cache */
 #define AMD_L3_EDX_C_SIZE(x)           ((((x) >> 18) & 0xffff) * 1024 * 512)
-#define AMD_L3_EDX_C_ASSOC(x)           (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_ASSOC(x)           (((x) >> 12) & 0xf)
 #define AMD_L3_EDX_C_LPT(x)             (((x) >> 8)  & 0xf)
 #define AMD_L3_EDX_C_LS(x)              ( (x)        & 0xff)