[src/trunk]: src/sys/arch/x86/x86 Fix wrong order; first enable WP, then enab...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0923e4b602ea
branches:  trunk
changeset: 321369:0923e4b602ea
user:      maxv <maxv%NetBSD.org@localhost>
date:      Tue Mar 13 16:52:42 2018 +0000

description:
Fix wrong order; first enable WP, then enable interrupts. Otherwise we
might get an interrupt before re-enabling WP, and be rescheduled as a
result. In practice it never happens, because the previous PSL always
has interrupts disabled too.

diffstat:

 sys/arch/x86/x86/patch.c |  8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diffs (32 lines):

diff -r d8d2fe3949a1 -r 0923e4b602ea sys/arch/x86/x86/patch.c
--- a/sys/arch/x86/x86/patch.c  Tue Mar 13 16:45:52 2018 +0000
+++ b/sys/arch/x86/x86/patch.c  Tue Mar 13 16:52:42 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: patch.c,v 1.33 2018/02/22 09:41:06 maxv Exp $  */
+/*     $NetBSD: patch.c,v 1.34 2018/03/13 16:52:42 maxv Exp $  */
 
 /*-
  * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.33 2018/02/22 09:41:06 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: patch.c,v 1.34 2018/03/13 16:52:42 maxv Exp $");
 
 #include "opt_lockdebug.h"
 #ifdef i386
@@ -182,10 +182,12 @@
        /* Write back and invalidate cache, flush pipelines. */
        wbinvd();
        x86_flush();
-       x86_write_psl(psl);
 
        /* Re-enable write protection. */
        lcr0(cr0);
+
+       /* Restore the PSL, potentially re-enabling interrupts. */
+       x86_write_psl(psl);
 }
 
 void