[src/trunk]: src/sys/arch/powerpc/include/oea add functions to access SCOM re...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f3c4c86bdde4
branches:  trunk
changeset: 323138:f3c4c86bdde4
user:      macallan <macallan%NetBSD.org@localhost>
date:      Fri Jun 01 18:18:11 2018 +0000

description:
add functions to access SCOM registers on 970 CPUs

diffstat:

 sys/arch/powerpc/include/oea/spr.h |  57 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 56 insertions(+), 1 deletions(-)

diffs (73 lines):

diff -r 85480da35211 -r f3c4c86bdde4 sys/arch/powerpc/include/oea/spr.h
--- a/sys/arch/powerpc/include/oea/spr.h        Fri Jun 01 18:14:33 2018 +0000
+++ b/sys/arch/powerpc/include/oea/spr.h        Fri Jun 01 18:18:11 2018 +0000
@@ -1,8 +1,17 @@
-/*     $NetBSD: spr.h,v 1.5 2018/05/04 16:57:14 macallan Exp $ */
+/*     $NetBSD: spr.h,v 1.6 2018/06/01 18:18:11 macallan Exp $ */
 
 #ifndef _POWERPC_OEA_SPR_H_
 #define        _POWERPC_OEA_SPR_H_
 
+#if !defined(_LOCORE) && defined(_KERNEL)
+#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
+
+#include <powerpc/psl.h>
+#include <powerpc/spr.h>
+
+#endif
+#endif
+
 /*
  * Special Purpose Register declarations.
  *
@@ -299,4 +308,50 @@
 #define        PMCN_TBLTRANS            3 /* TBL bit transitions */
 #define        PCMN_IDISPATCH           4 /* Instructions dispatched */
 
+#if !defined(_LOCORE) && defined(_KERNEL)
+
+#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64)
+
+static inline uint64_t
+scom_read(register_t address)
+{
+       register_t msr;
+       uint64_t ret;
+
+       msr = mfmsr();
+       mtmsr(msr & ~PSL_EE);
+       __asm volatile("isync;");
+
+       mtspr(SPR_SCOMC, address | SCOMC_READ);
+       __asm volatile("isync;");
+
+       ret = mfspr(SPR_SCOMD);
+       mtmsr(msr);
+       __asm volatile("isync;");
+
+       return ret;
+}
+
+static inline void
+scom_write(register_t address, uint64_t data)
+{
+       register_t msr;
+
+       msr = mfmsr();
+       mtmsr(msr & ~PSL_EE);
+       __asm volatile("isync;");
+
+       mtspr(SPR_SCOMD, data);
+       __asm volatile("isync;");
+       mtspr(SPR_SCOMC, address | SCOMC_WRITE);
+       __asm volatile("isync;");
+       
+       mtmsr(msr);
+       __asm volatile("isync;");
+}
+
+#endif /* defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) */
+
+#endif /* !defined(_LOCORE) && defined(_KERNEL) */
+
 #endif /* !_POWERPC_SPR_H_ */