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[src/trunk]: src/sys/arch/arm/omap Consistently use #define<tab>
details: https://anonhg.NetBSD.org/src/rev/134719cd594f
branches: trunk
changeset: 328447:134719cd594f
user: matt <matt%NetBSD.org@localhost>
date: Thu Apr 03 17:09:48 2014 +0000
description:
Consistently use #define<tab>
diffstat:
sys/arch/arm/omap/omap2_reg.h | 756 +++++++++++++++++++++---------------------
1 files changed, 378 insertions(+), 378 deletions(-)
diffs (truncated from 991 to 300 lines):
diff -r 209163eacb00 -r 134719cd594f sys/arch/arm/omap/omap2_reg.h
--- a/sys/arch/arm/omap/omap2_reg.h Thu Apr 03 17:07:11 2014 +0000
+++ b/sys/arch/arm/omap/omap2_reg.h Thu Apr 03 17:09:48 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.24 2014/03/29 23:32:41 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.25 2014/04/03 17:09:48 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -30,7 +30,7 @@
*/
#ifndef _ARM_OMAP_OMAP2_REG_H_
-#define _ARM_OMAP_OMAP2_REG_H_
+#define _ARM_OMAP_OMAP2_REG_H_
#include "opt_omap.h"
@@ -41,132 +41,132 @@
/*
* L4 Interconnect WAKEUP address space
*/
-#define OMAP2430_L4_CORE_BASE 0x48000000
-#define OMAP2430_L4_CORE_SIZE (16 << 20) /* 16 MB */
+#define OMAP2430_L4_CORE_BASE 0x48000000
+#define OMAP2430_L4_CORE_SIZE (16 << 20) /* 16 MB */
-#define OMAP2430_L4_WAKEUP_BASE 0x49000000
-#define OMAP2430_L4_WAKEUP_SIZE (8 << 20) /* 8 MB */
+#define OMAP2430_L4_WAKEUP_BASE 0x49000000
+#define OMAP2430_L4_WAKEUP_SIZE (8 << 20) /* 8 MB */
-#define OMAP3430_L4_CORE_BASE 0x48000000
-#define OMAP3430_L4_CORE_SIZE 0x01000000 /* 16 MB */
+#define OMAP3430_L4_CORE_BASE 0x48000000
+#define OMAP3430_L4_CORE_SIZE 0x01000000 /* 16 MB */
-#define OMAP3530_L4_CORE_BASE 0x48000000
-#define OMAP3530_L4_CORE_SIZE 0x01000000 /* 16 MB */
+#define OMAP3530_L4_CORE_BASE 0x48000000
+#define OMAP3530_L4_CORE_SIZE 0x01000000 /* 16 MB */
/* OMAP3 processors */
-#define OMAP3430_L4_WAKEUP_BASE 0x48300000
-#define OMAP3430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP3430_L4_WAKEUP_BASE 0x48300000
+#define OMAP3430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP3430_L4_PERIPHERAL_BASE 0x49000000
-#define OMAP3430_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
+#define OMAP3430_L4_PERIPHERAL_BASE 0x49000000
+#define OMAP3430_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
-#define OMAP3430_L4_EMULATION_BASE 0x54000000
-#define OMAP3430_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define OMAP3430_L4_EMULATION_BASE 0x54000000
+#define OMAP3430_L4_EMULATION_SIZE 0x00800000 /* 8MB */
-#define OMAP3530_L4_WAKEUP_BASE 0x48300000
-#define OMAP3530_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP3530_L4_WAKEUP_BASE 0x48300000
+#define OMAP3530_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP3530_L4_PERIPHERAL_BASE 0x49000000
-#define OMAP3530_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
+#define OMAP3530_L4_PERIPHERAL_BASE 0x49000000
+#define OMAP3530_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
-#define OMAP3530_L4_EMULATION_BASE 0x54000000
-#define OMAP3530_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define OMAP3530_L4_EMULATION_BASE 0x54000000
+#define OMAP3530_L4_EMULATION_SIZE 0x00800000 /* 8MB */
/* OMAP4 processors */
-#define OMAP4430_L4_CORE_BASE 0x4A000000
-#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
+#define OMAP4430_L4_CORE_BASE 0x4A000000
+#define OMAP4430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
-#define OMAP4430_L4_WAKEUP_BASE 0x4A300000
-#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+#define OMAP4430_L4_WAKEUP_BASE 0x4A300000
+#define OMAP4430_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
-#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000
-#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define OMAP4430_L4_PERIPHERAL_BASE 0x48000000
+#define OMAP4430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
-#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
+#define OMAP4430_L4_ABE_BASE 0x49000000 /* Actually L3 */
+#define OMAP4430_L4_ABE_SIZE 0x01000000 /* 16MB */
-#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
-#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP4430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP4430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
-#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
-#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
/* OMAP5 processors */
-#define OMAP5430_L4_CORE_BASE 0x4A000000
-#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
+#define OMAP5430_L4_CORE_BASE 0x4A000000
+#define OMAP5430_L4_CORE_SIZE 0x01000000 /* 16MB - CFG */
-#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
-#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
+#define OMAP5430_L4_WAKEUP_BASE 0x4AE00000
+#define OMAP5430_L4_WAKEUP_SIZE 0x00200000 /* 2M */
-#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
-#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define OMAP5430_L4_PERIPHERAL_BASE 0x48000000
+#define OMAP5430_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
-#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
+#define OMAP5430_L4_ABE_BASE 0x49000000 /* Actually L3 */
+#define OMAP5430_L4_ABE_SIZE 0x01000000 /* 16MB */
-#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
-#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP5430_EMIF1_BASE 0x4C000000 /* MemCtrl 0 */
+#define OMAP5430_EMIF1_SIZE 0x00100000 /* 4KB padded to 1M */
-#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
-#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP5430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
+#define OMAP5430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
/* TI Sitara AM335x (OMAP like) */
-#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
-#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */
+#define TI_AM335X_L4_WAKEUP_BASE 0x44C00000
+#define TI_AM335X_L4_WAKEUP_SIZE 0x00400000 /* 4MB */
-#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000
-#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define TI_AM335X_L4_PERIPHERAL_BASE 0x48000000
+#define TI_AM335X_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define TI_AM335X_L4_FAST_BASE 0x4A000000
-#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
+#define TI_AM335X_L4_FAST_BASE 0x4A000000
+#define TI_AM335X_L4_FAST_SIZE 0x01000000 /* 16MB */
-#define TI_AM335X_EMIF1_BASE 0x4C000000
-#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
+#define TI_AM335X_EMIF1_BASE 0x4C000000
+#define TI_AM335X_EMIF1_SIZE 0x00100000 /* 4KB pad to 1MB */
/* TI Sitara DM37xx (OMAP like) */
-#define TI_DM37XX_L4_CORE_BASE 0x48000000
-#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */
+#define TI_DM37XX_L4_CORE_BASE 0x48000000
+#define TI_DM37XX_L4_CORE_SIZE 0x01000000 /* 16MB */
-#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000
-#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */
+#define TI_DM37XX_L4_WAKEUP_BASE 0x48300000
+#define TI_DM37XX_L4_WAKEUP_SIZE 0x00010000 /* 64KB */
-#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000
-#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
+#define TI_DM37XX_L4_PERIPHERAL_BASE 0x49000000
+#define TI_DM37XX_L4_PERIPHERAL_SIZE 0x01000000 /* 16MB */
-#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
-#define TI_DM37XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
+#define TI_DM37XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
/*
* Clock Management registers base, offsets, and size
*/
#ifdef OMAP_2430
-#define OMAP2_CM_BASE 0x49006000
+#define OMAP2_CM_BASE 0x49006000
#endif
#ifdef OMAP_2420
-#define OMAP2_CM_BASE 0x48008000
+#define OMAP2_CM_BASE 0x48008000
#endif
#ifdef OMAP_3430
-#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP3430_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_3530
-#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP3530_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_4430
-#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP4430_L4_CORE_BASE + 0x04000)
#endif
#ifdef OMAP_5430
-#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
+#define OMAP2_CM_BASE (OMAP5430_L4_CORE_BASE + 0x04000)
#endif
#ifdef TI_AM335X
-#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
+#define OMAP2_CM_BASE (TI_AM335X_L4_WAKEUP_BASE + 0x200000)
#endif
#ifdef TI_DM37XX
-#define OMAP2_CM_BASE 0x48004000
+#define OMAP2_CM_BASE 0x48004000
#endif
#define OMAP2_CM_CLKSEL_MPU 0x140
@@ -175,7 +175,7 @@
#define OMAP2_CM_ICLKEN1_CORE 0x210
#define OMAP2_CM_ICLKEN2_CORE 0x214
#define OMAP2_CM_CLKSEL2_CORE 0x244
-#define OMAP3_CM_IDLEST1_CORE 0xa20
+#define OMAP3_CM_IDLEST1_CORE 0xa20
#define OMAP2_CM_SIZE (0x1000)
/*
@@ -187,38 +187,38 @@
/*
* bit defines for OMAP2_CM_FCLKEN2_CORE
*/
-#define OMAP2_CM_FCLKEN1_CORE_EN_DSS1 __BIT(0)
-#define OMAP2_CM_FCLKEN1_CORE_EN_DSS2 __BIT(1)
-#define OMAP2_CM_FCLKEN1_CORE_EN_TV __BIT(2)
-#define OMAP2_CM_FCLKEN1_CORE_RESa __BIT(3)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT2 __BIT(4)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT3 __BIT(5)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT4 __BIT(6)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT5 __BIT(7)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT6 __BIT(8)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT7 __BIT(9)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT8 __BIT(10)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT9 __BIT(11)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT10 __BIT(12)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT11 __BIT(13)
-#define OMAP2_CM_FCLKEN1_CORE_EN_GPT12 __BIT(14)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP1 __BIT(15)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP2 __BIT(16)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI1 __BIT(17)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI2 __BIT(18)
-#define OMAP2_CM_FCLKEN1_CORE_RESb __BITS(20,19)
-#define OMAP2_CM_FCLKEN1_CORE_EN_UART1 __BIT(21)
-#define OMAP2_CM_FCLKEN1_CORE_EN_UART2 __BIT(22)
-#define OMAP2_CM_FCLKEN1_CORE_EN_HDQ __BIT(23)
-#define OMAP2_CM_FCLKEN1_CORE_RESc __BIT(24)
-#define OMAP2_CM_FCLKEN1_CORE_EN_FAC __BIT(25)
-#define OMAP2_CM_FCLKEN1_CORE_RESd __BIT(26)
-#define OMAP2_CM_FCLKEN1_CORE_EN_MSPRO __BIT(27)
-#define OMAP2_CM_FCLKEN1_CORE_RESe __BIT(28)
-#define OMAP2_CM_FCLKEN1_CORE_EN_WDT4 __BIT(29)
-#define OMAP2_CM_FCLKEN1_CORE_RESf __BIT(30)
-#define OMAP2_CM_FCLKEN1_CORE_EN_CAM __BIT(31)
-#define OMAP2_CM_FCLKEN1_CORE_RESV \
+#define OMAP2_CM_FCLKEN1_CORE_EN_DSS1 __BIT(0)
+#define OMAP2_CM_FCLKEN1_CORE_EN_DSS2 __BIT(1)
+#define OMAP2_CM_FCLKEN1_CORE_EN_TV __BIT(2)
+#define OMAP2_CM_FCLKEN1_CORE_RESa __BIT(3)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT2 __BIT(4)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT3 __BIT(5)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT4 __BIT(6)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT5 __BIT(7)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT6 __BIT(8)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT7 __BIT(9)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT8 __BIT(10)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT9 __BIT(11)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT10 __BIT(12)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT11 __BIT(13)
+#define OMAP2_CM_FCLKEN1_CORE_EN_GPT12 __BIT(14)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP1 __BIT(15)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCBSP2 __BIT(16)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI1 __BIT(17)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MCSPI2 __BIT(18)
+#define OMAP2_CM_FCLKEN1_CORE_RESb __BITS(20,19)
+#define OMAP2_CM_FCLKEN1_CORE_EN_UART1 __BIT(21)
+#define OMAP2_CM_FCLKEN1_CORE_EN_UART2 __BIT(22)
+#define OMAP2_CM_FCLKEN1_CORE_EN_HDQ __BIT(23)
+#define OMAP2_CM_FCLKEN1_CORE_RESc __BIT(24)
+#define OMAP2_CM_FCLKEN1_CORE_EN_FAC __BIT(25)
+#define OMAP2_CM_FCLKEN1_CORE_RESd __BIT(26)
+#define OMAP2_CM_FCLKEN1_CORE_EN_MSPRO __BIT(27)
+#define OMAP2_CM_FCLKEN1_CORE_RESe __BIT(28)
+#define OMAP2_CM_FCLKEN1_CORE_EN_WDT4 __BIT(29)
+#define OMAP2_CM_FCLKEN1_CORE_RESf __BIT(30)
+#define OMAP2_CM_FCLKEN1_CORE_EN_CAM __BIT(31)
+#define OMAP2_CM_FCLKEN1_CORE_RESV \
(OMAP2_CM_FCLKEN1_CORE_RESa \
|OMAP2_CM_FCLKEN1_CORE_RESb \
|OMAP2_CM_FCLKEN1_CORE_RESc \
@@ -230,25 +230,25 @@
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