[src/trunk]: src/sys/arch/arm/arm32 Deal with ASID tagged VIVT icaches (not t...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/70337c343def
branches:  trunk
changeset: 328635:70337c343def
user:      matt <matt%NetBSD.org@localhost>
date:      Fri Apr 11 02:39:03 2014 +0000

description:
Deal with ASID tagged VIVT icaches (not that we have any cpus with them but...)

diffstat:

 sys/arch/arm/arm32/arm32_tlb.c |  24 +++++++++++++++++++++---
 1 files changed, 21 insertions(+), 3 deletions(-)

diffs (56 lines):

diff -r 67b2bfddb8d8 -r 70337c343def sys/arch/arm/arm32/arm32_tlb.c
--- a/sys/arch/arm/arm32/arm32_tlb.c    Fri Apr 11 02:37:45 2014 +0000
+++ b/sys/arch/arm/arm32/arm32_tlb.c    Fri Apr 11 02:39:03 2014 +0000
@@ -27,7 +27,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.1 2014/03/28 21:51:21 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.2 2014/04/11 02:39:03 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -58,9 +58,18 @@
 void
 tlb_invalidate_all(void)
 {
+       const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
        arm_dsb();
        armreg_tlbiall_write(0);
        arm_isb();
+       if (__predict_false(vivt_icache_p)) {
+               if (arm_has_tlbiasid_p) {
+                       armreg_icialluis_write(0);
+               } else {
+                       armreg_iciallu_write(0);
+               }
+       }
+       arm_isb();
 }
 
 void
@@ -72,13 +81,22 @@
 void
 tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
 {
+       const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
        arm_dsb();
        if (arm_has_tlbiasid_p) {
-               armreg_tlbiall_write(0);
-       } else {
                for (; lo <= hi; lo++) {
                        armreg_tlbiasid_write(lo);
                }
+               arm_isb();
+               if (__predict_false(vivt_icache_p)) {
+                       armreg_icialluis_write(0);
+               }
+       } else {
+               armreg_tlbiall_write(0);
+               arm_isb();
+               if (__predict_false(vivt_icache_p)) {
+                       armreg_iciallu_write(0);
+               }
        }
        arm_isb();
 }