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[src/trunk]: src/sys/dev/pci Print the CRS Software Visibility Enable bit and...
details: https://anonhg.NetBSD.org/src/rev/0451b52e2c24
branches: trunk
changeset: 329118:0451b52e2c24
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri May 09 14:51:26 2014 +0000
description:
Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.
diffstat:
sys/dev/pci/pci_subr.c | 8 ++++++--
sys/dev/pci/pcireg.h | 3 ++-
2 files changed, 8 insertions(+), 3 deletions(-)
diffs (53 lines):
diff -r ea3a1a16971d -r 0451b52e2c24 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri May 09 11:51:49 2014 +0000
+++ b/sys/dev/pci/pci_subr.c Fri May 09 14:51:26 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.107 2014/05/09 14:51:26 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.107 2014/05/09 14:51:26 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -1245,6 +1245,8 @@
printf(" SERR on Fatal Error Enable\n");
if ((reg & PCIE_RCR_PME_IE) != 0)
printf(" PME Interrupt Enable\n");
+ if ((reg & PCIE_RCR_CRS_SVE) != 0)
+ printf(" CRS Software Visibility Enable\n");
/* Root Capability Register */
printf(" Root Capability Register: %04x\n",
@@ -1357,6 +1359,8 @@
if (((val >> i) & 0x01) != 0)
printf(" %sGT/s", linkspeeds[i]);
}
+ printf(" Crosslink Supported: %s\n",
+ (reg & PCIE_LCAP2_CROSSLNK) != 0 ? "yes" : "no");
printf("\n");
/* Link Control 2 */
diff -r ea3a1a16971d -r 0451b52e2c24 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Fri May 09 11:51:49 2014 +0000
+++ b/sys/dev/pci/pcireg.h Fri May 09 14:51:26 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.85 2014/03/29 19:28:25 christos Exp $ */
+/* $NetBSD: pcireg.h,v 1.86 2014/05/09 14:51:26 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -751,6 +751,7 @@
#define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */
#define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */
#define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */
+#define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */
#define PCIE_RSR 0x20 /* Root Status Register */
#define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */
#define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */
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